From da3496d9d6f36ea829b7f74b05a4d72dcd501203 Mon Sep 17 00:00:00 2001
From: Lucas Weaver <l-weaver@ti.com>
Date: Fri, 28 Jan 2022 14:17:20 -0600
Subject: [PATCH] arm64 dts ti k3 j721e: Changes for enabling HW PWM on J721e
SK platform
The following has been done in this commit:
1) Add new nodes definitions for enabling all 6 EHRPWM instances
2) Add rules to disable all the instances for non SK platforms
3) Add rules to enable instances 2 and 3 for the SK platform
4) Add mux settings for enabling channel A from instances 2 and 3
for the RPi extension header on the SK platform
---
.../dts/ti/k3-j721e-common-proc-board.dts | 24 ++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 62 +++++++++++++-
.../dts/ti/k3-j721e-sk-rpi-exp-header.dts | 82 ++++++++++++-------
arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 24 ++++++
4 files changed, 160 insertions(+), 32 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index d9262920fcf4f..ef80fe26c62f6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -1192,3 +1192,27 @@ &csi0_port3 {
&csi0_port4 {
status = "disabled";
};
+
+&main_ehrpwm0 {
+ status = "disabled";
+};
+
+&main_ehrpwm1 {
+ status = "disabled";
+};
+
+&main_ehrpwm2 {
+ status = "disabled";
+};
+
+&main_ehrpwm3 {
+ status = "disabled";
+};
+
+&main_ehrpwm4 {
+ status = "disabled";
+};
+
+&main_ehrpwm5 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 3151815c02bb4..59b1042c4726f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -72,7 +72,67 @@ usb_serdes_mux: mux-controller@4000 {
#mux-control-cells = <1>;
mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
- };
+ };
+
+ ehrpwm_tbclk: clock@4140 {
+ compatible = "ti,am654-ehrpwm-tbclk", "syscon";
+ reg = <0x4140 0x18>;
+ #clock-cells = <1>;
+ };
+ };
+
+ main_ehrpwm0: pwm@3000000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3000000 0x0 0x100>;
+ power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm1: pwm@3010000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3010000 0x0 0x100>;
+ power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm2: pwm@3020000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3020000 0x0 0x100>;
+ power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm3: pwm@3030000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3030000 0x0 0x100>;
+ power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm4: pwm@3040000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3040000 0x0 0x100>;
+ power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
+ clock-names = "tbclk", "fck";
+ };
+
+ main_ehrpwm5: pwm@3050000 {
+ compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x3050000 0x0 0x100>;
+ power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
+ clock-names = "tbclk", "fck";
};
gic500: interrupt-controller@1800000 {
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk-rpi-exp-header.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk-rpi-exp-header.dts
index 1536a33b07db3..d6751abed09b9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk-rpi-exp-header.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk-rpi-exp-header.dts
@@ -22,29 +22,27 @@ J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */
rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default {
pinctrl-single,pins = <
- J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
- J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AD28) PRG0_PRU1_GPO8.GPIO0_71 */
- J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO19.GPIO0_82 */
- J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
- J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
- J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
- J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
- J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */
- J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
- J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
- J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
- J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */
- J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
- J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
- J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
- J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
- J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
- J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
- J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
- J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */
- J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
- J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
- J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
+ J721E_IOPAD(0x01C, PIN_OUTPUT_PULLDOWN, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */
+ J721E_IOPAD(0x120, PIN_OUTPUT_PULLDOWN, 7) /* (AD28) PRG0_PRU1_GPO8.GPIO0_71 */
+ J721E_IOPAD(0x14C, PIN_OUTPUT_PULLDOWN, 7) /* (AD29) PRG0_PRU1_GPO19.GPIO0_82 */
+ J721E_IOPAD(0x02C, PIN_OUTPUT_PULLDOWN, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */
+ J721E_IOPAD(0x198, PIN_OUTPUT_PULLDOWN, 7) /* (V25) RGMII6_TD1.GPIO0_101 */
+ J721E_IOPAD(0x1B0, PIN_OUTPUT_PULLDOWN, 7) /* (W24) RGMII6_RD1.GPIO0_107 */
+ J721E_IOPAD(0x1A0, PIN_OUTPUT_PULLDOWN, 7) /* (W29) RGMII6_TXC.GPIO0_103 */
+ J721E_IOPAD(0x17C, PIN_OUTPUT_PULLDOWN, 7) /* (U24) RGMII5_RD2.GPIO0_94 */
+ J721E_IOPAD(0x190, PIN_OUTPUT_PULLDOWN, 7) /* (W23) RGMII6_TD3.GPIO0_99 */
+ J721E_IOPAD(0x008, PIN_OUTPUT_PULLDOWN, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */
+ J721E_IOPAD(0x1D0, PIN_OUTPUT_PULLDOWN, 7) /* (AA3) SPI0_D1.GPIO0_115 */
+ J721E_IOPAD(0x11C, PIN_OUTPUT_PULLDOWN, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
+ J721E_IOPAD(0x148, PIN_OUTPUT_PULLDOWN, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */
+ J721E_IOPAD(0x004, PIN_OUTPUT_PULLDOWN, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */
+ J721E_IOPAD(0x014, PIN_OUTPUT_PULLDOWN, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */
+ J721E_IOPAD(0x020, PIN_OUTPUT_PULLDOWN, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */
+ J721E_IOPAD(0x19C, PIN_OUTPUT_PULLDOWN, 7) /* (W27) RGMII6_TD0.GPIO0_102 */
+ J721E_IOPAD(0x1B4, PIN_OUTPUT_PULLDOWN, 7) /* (W25) RGMII6_RD0.GPIO0_108 */
+ J721E_IOPAD(0x188, PIN_OUTPUT_PULLDOWN, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */
+ J721E_IOPAD(0x00C, PIN_OUTPUT_PULLDOWN, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */
+ J721E_IOPAD(0x010, PIN_OUTPUT_PULLDOWN, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */
>;
};
@@ -53,24 +51,46 @@ rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default {
J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */
>;
};
+
+ rpi_header_ehrpwm2_pins_default: rpi-header-ehrpwm2-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x178, PIN_OUTPUT_PULLDOWN, 6) /* (U27) RGMII5_RD3.EHRPWM2_A */
+ >;
+ };
+
+ rpi_header_ehrpwm3_pins_default: rpi-header-ehrpwm3-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x18C, PIN_OUTPUT_PULLDOWN, 6) /* (V23) RGMII6_RX_CTL.EHRPWM3_A */
+ >;
+ };
};
&main_gpio0 {
- pinctrl-names = "default";
- pinctrl-0 = <&rpi_header_gpio0_pins_default>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_gpio0_pins_default>;
};
&main_gpio1 {
- pinctrl-names = "default";
- pinctrl-0 = <&rpi_header_gpio1_pins_default>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_gpio1_pins_default>;
};
&main_i2c5 {
- pinctrl-names = "default";
- pinctrl-0 = <&main_i2c5_pins_default>;
- clock-frequency = <400000>;
- status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c5_pins_default>;
+ clock-frequency = <400000>;
+ status = "okay";
};
+&main_ehrpwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_ehrpwm2_pins_default>;
+ status = "okay";
+};
+&main_ehrpwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rpi_header_ehrpwm3_pins_default>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 3038723afb9c1..f6203e96a7196 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -1314,3 +1314,27 @@ &c71_0 {
memory-region = <&c71_0_dma_memory_region>,
<&c71_0_memory_region>;
};
+
+&main_ehrpwm0 {
+ status = "disabled";
+};
+
+&main_ehrpwm1 {
+ status = "disabled";
+};
+
+&main_ehrpwm2 {
+ status = "disabled";
+};
+
+&main_ehrpwm3 {
+ status = "disabled";
+};
+
+&main_ehrpwm4 {
+ status = "disabled";
+};
+
+&main_ehrpwm5 {
+ status = "disabled";
+};
--
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