- Oct 06, 2022
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Jayesh Choudhary authored
crypto driver itself is not dma-coherent. So drop it. Fixes: b366b240 ('arm64: dts: ti: k3-am6: Add crypto accelarator node') Signed-off-by:
Jayesh Choudhary <j-choudhary@ti.com>
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Jayesh Choudhary authored
crypto driver itself is not dma-coherent. It is the system-dma that moves data and so 'dma-coherent' property should be dropped. Fixes: 2ce9a729 ('dt-bindings: crypto: Add TI SA2UL crypto accelerator documentation') Signed-off-by:
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- Sep 30, 2022
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : arm64: dts: ti: k3-j784s4-evm: Add DP1 arm64: dts: ti: k3-j784s4-evm: add DSI to eDP arm64: dts: ti: k3-j784s4-main: add DSI & DSI PHY drm/bridge: ti-sn65dsi86: Fix unbalanced pm_runtime state arm64: dts: ti: k3-j784s4-evm: Add DP0 arm64: dts: ti: k3-j784s4-*: add DP & DP PHY arm64: dts: ti: k3-j784s4-*: Add DSS node arm64: dts: ti: k3-j784s4-main: Enable crypto accelerator dmaengine: ti: k3-psil-j784s4: Add psil threads for sa2ul Signed-off-by:
LCPD Auto Merger <lcpd_integration@list.ti.com>
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Add the endpoint nodes to describe connection from DSS => DSI Bridge => DSI to eDP bridge => eDP panel. Also set status of all the required nodes for DP1 as okay Signed-off-by:
Rahul T R <r-ravikumar@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Add DT nodes for DSI to eDP bridge. The DSI to edp bridge is sn65dsi86 on the board Signed-off-by:
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Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper. Signed-off-by:
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The commit 016204fe ("drm/bridge: ti-sn65dsi86: Detect id panel is connected") has added a pm_runtime_get_sync() call in the ti_sn_aux_transfer() function, and is expected to unwind before returning from the function. The logic erroneously added another pm_runtime_get_sync() instead of a pm_runtime_put_sync() call. Fix this. Fixes: 016204fe ("drm/bridge: ti-sn65dsi86: Detect id panel is connected") Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
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Add the endpoint nodes to describe connection from DSS => MHDP => DisplayPort connector. Also add the required nodes gpio expander 4 and pinmux for main_i2c4 which is required for controlling DP Power and set status of all the required nodes for DP0 as okay Signed-off-by:
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Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. Also add pinmux required for DP HPD. Signed-off-by:
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Add DSS node for J784S4 SoC. DSS IP in J784S4 is same as DSS IP in J721E, so same compatible is being used. Also add assigned clks for DSS Signed-off-by:
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Add the node for sa2ul crypto accelerator. Signed-off-by:
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Add endpoint configuration for the four ingress and two egress threads for main domain crypto accelerator. Signed-off-by:
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : (21 commits) arm64: dts: ti: k3-j784s4-evm: Enable TCA4608 I2C GPIO expander on main_i2c5 arm64: dts: ti: Add an overlay for Fusion board on J784S4 arm64: dts: ti: k3-j784s4-evm: Enable CSI2RX and corresponding DPHY instances arm64: dts: ti: k3-j784s4-evm: Enable main_i2c5 arm64: dts: ti: k3-j784s4-main: Add CSI2RX nodes arm64: dts: ti: k3-j784s4: Add initial PCIe/SerDes support for J784S4 arm64: dts: ti: k3-j784s4: Add overlay to enable CPSW9G ports in QSGMII mode arm64: dts: ti: j784s4-evm: Enable EthFw arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G arm64: dts: ti: k3-j784s4-mcu: Cleanup mcu_cpsw node arm64: dts: ti: k3-j784s4: Add MAIN CPSW2G node arm64: dts: ti: k3-j784s4: Add CPSW9G nodes arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes arm64: dts: ti: k3-j784s4-main: Add system controller node and SERDES lane mux net: ethernet: ti: am65-cpsw: Add support for J784s4 CPSW9G phy: ti: phy-gmii-sel: Add support for CPSW9G GMII SEL in J784s4 dmaengine: ti: k3-psil: Add PSI-L thread support for J784s4 soc: ti: k3-socinfo: Add entry for J784S4 SoC family dt-bindings: net: ti: k3-am654-cpsw-nuss: Update bindings for J784S4 CPSW9G dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J784S4 ... Signed-off-by:
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Enable the TCA5608 I2C GPIO expander on main_i2c5 which provides the CSI2 expansion GPIOs on J784S4 EVM. Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by:
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The ADAS Sensor Fusion Application board can be used with J784S4 to connect up to 8 2MP cameras. Signed-off-by:
Pratyush Yadav <p.yadav@ti.com> Signed-off-by:
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CSI2RX and corresponding DPHY instances were disabled in the j784s4-main.dtsi, enable these instances. Signed-off-by:
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Enable the I2C instance and add pinmux entries for main_i2c5 which is the camera control interface for CSI. Signed-off-by:
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Add the entries for two CSI2RX instances and corresponding DPHY for J784S4 and keep them disabled by default. Signed-off-by:
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J784S4 SoC supports two PCIE instances as follows: * PCIE0 - 4x lanes * PCIE1 - 4x lanes J784S4 EVM board has the following PCIE connectors: * PCIE0 - 4x lanes * PCIE1 - 2x lanes Signed-off-by:
Matt Ranostay <mranostay@ti.com> Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by:
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The J7 Quad Port Add-On Ethernet Card for J784s4 Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode. Add support to reset PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses directly from U-Boot. Disable cpsw9g_virt_mac node in device-tree since native ethernet driver supports CPSW2G and CPSW9G. Replace j784s4-main-r5f0_0-fw which currently points to EthFw, with: pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f which is currently unused, to ensure that EthFw is not loaded. Signed-off-by:
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Add CPSW9G virt-mac nodes required by EthFw and enable the following nodes main_udmass_inta, main_ringacc and main_udmap required for communication between EthFw and virt-mac driver. Assign SerDes lane mapping required by EthFw. EthFw will be enabled by default with these changes. Signed-off-by:
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Enable MCU CPSW2G Signed-off-by:
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Cleanup mcu_cpsw node, by deleting "status = disabled" present within the "mdio@f00", "cpts@3d000" and "phy@4040" nodes for the following reasons: - Since the outer mcu_cpsw node is disabled by default, the inner "mdio@f00" and "cpts@3d000" nodes will also be disabled. - When the mcu_cpsw node is enabled, the "mdio@f00" node is also required to be enabled by default. - The "cpts@3d000" node does not have a label, so it will not be possible to enable it selectively when the mcu_cpsw node is enabled. - The "phy@4040" node is not a device. The cleanup will make the mcu_cpsw node similar to the main_cpsw0 and main_cpsw1 nodes. Signed-off-by:
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Add CPSW2G device tree node for the main domain CPSW2G and enable it. Signed-off-by:
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Add CPSW9G nodes. Signed-off-by:
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Add DT nodes for all instances of WIZ and SERDES modules. Signed-off-by:
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The system controller node manages the CTRL_MMR0 region. Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. Signed-off-by:
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CPSW9G in J784s4 supports modes such as QSGMII. Add a new compatible for it. Signed-off-by:
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Each of the CPSW9G ports in J784s4 supports modes such as QSGMII. Add a new compatible for it and extend the qsgmii-main-ports support for J784s4. Signed-off-by:
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Add psil thread IDs for J784s4 and include J784s4 in the set of "k3_soc_devices" in k3-psil.c. Signed-off-by:
Apurva Nandan <a-nandan@ti.com> Signed-off-by:
Hari Nagalla <hnagalla@ti.com> Signed-off-by:
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J784S4 SoC's JTAG PARTNO is 0xBB80. Signed-off-by:
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Update bindings for TI K3 J784S4 SoC which contains 9 ports (8 external ports) CPSW9G module and add compatible for it. Signed-off-by:
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TI's J784S4 SoC supports additional PHY modes like QSGMII. Add a compatible for it. Enable the use of "ti,qsgmii-main-ports" property for J784S4. Signed-off-by:
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There are 4 lanes in the single instance of J784S4 SERDES. Each SERDES lane mux can select upto 4 different IPs. Define all the possible functions. Signed-off-by:
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- Sep 28, 2022
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LCPD Auto Merger authored
TI-Feature: rpmsg TI-Branch: rpmsg-ti-linux-5.10.y-intg * 'rpmsg-ti-linux-5.10.y-intg' of git://git.ti.com/rpmsg/rpmsg : arm64: dts: ti: Enable remote procs on J784S4 EVM arm64: dts: ti: k3-j784s4-mcu: Add MCU domain R5F cluster node arm64: dts: ti: k3-j784s4-main: Add MAIN domain R5F cluster and C7x nodes Signed-off-by:
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : phy: cdns-dphy: Fix common module reset logic Signed-off-by:
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Hari Nagalla authored
Enable R5F and C7x DSP device nodes and also set the IPC shared memory careveouts. These should match with the IPC and external memory sections of the remote processor FW binary. Signed-off-by: -
Hari Nagalla authored
The J784S4 SoCs have 4 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining three clusters are present in the MAIN domain (MAIN_R5FSS0, MAIN_R5FSS1 & MAIN_R5FSS2). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. The inter-processor communication between the main A72 cores and the R5F, C71x processors is achieved through shared memory and mailbox. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MCU R5FSS0 Core0: j784s4-mcu-r5f0_0-fw (both in LockStep and Split modes) MCU R5FSS0 Core1: j784s4-mcu-r5f0_1-fw (needed only in Split mode) Signed-off-by: -
Hari Nagalla authored
The J784S4 SoCs have 4 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining three clusters are present in the MAIN domain (MAIN_R5FSS0, MAIN_R5FSS1 & MAIN_R5FSS2). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. And in addition there are four C7x DSP subsystems in the MAIN voltage domain. The inter-processor communication between the main A72 cores and the R5F, C71x processors is achieved through shared memory and mailbox. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MAIN R5FSS0 Core0: j784s4-main-r5f0_0-fw (both in LockStep and Split modes) MAIN R5FSS0 Core1: j784s4-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: j784s4-main-r5f1_0-fw (both in LockStep and Split modes) MAIN R5FSS1 Core1: j784s4-main-r5f1_1-fw (needed only in Split mode) MAIN R5FSS2 Core0: j784s4-main-r5f2_0-fw (both in LockStep and Split modes) MAIN R5FSS2 Core1: j784s4-main-r5f2_1-fw (needed only in Split mode) C71x_0 DSP : j784s4-c71_0-fw C71x_1 DSP : j784s4-c71_1-fw C71x_2 DSP : j784s4-c71_2-fw C71x_3 DSP : j784s4-c71_3-fw Signed-off-by: -
While inverting the logic for SoC specific common module reset, the DPHY_LANE_RESET_CMN_EN was performed only when soc_device_match() returns match, but since the newer SoCs has been removed from the table, this causes issue with streaming for newer SoCs.This commit fixes the common module reset properly to not issue software reset only for J721E SR1.0 and issue software RSTB_CMN for all other new platforms. Fixes: 0f25c348 ("phy: cdns-dphy: Update common module reset logic for newer platforms") Signed-off-by:
Jai Luthra <j-luthra@ti.com> Signed-off-by:
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