From 94b92c07ca29b1527ea9ff1ab94a3943667b89c1 Mon Sep 17 00:00:00 2001
From: Deepak Khatri <lorforlinux@beagleboard.org>
Date: Wed, 29 Nov 2023 19:26:36 +0530
Subject: [PATCH] Restructure AI-64 chapters
---
boards/beaglebone/ai-64/01-introduction.rst | 168 +
.../ai-64/{ch03.rst => 02-quick-start.rst} | 156 +-
.../ai-64/03-design-and-specifications.rst | 3893 +++++++++++++++++
...ch07.rst => 04-connectors-and-pinouts.rst} | 1 +
.../ai-64/05-demos-and-tutorials.rst | 0
boards/beaglebone/ai-64/06-support.rst | 213 +
boards/beaglebone/ai-64/ch01.rst | 18 -
boards/beaglebone/ai-64/ch02.rst | 49 -
boards/beaglebone/ai-64/ch04.rst | 201 -
boards/beaglebone/ai-64/ch05.rst | 315 --
boards/beaglebone/ai-64/ch06.rst | 1707 --------
boards/beaglebone/ai-64/ch08.rst | 1835 --------
boards/beaglebone/ai-64/ch09.rst | 41 -
boards/beaglebone/ai-64/ch10.rst | 40 -
boards/beaglebone/ai-64/ch11.rst | 69 -
boards/beaglebone/ai-64/index.rst | 15 +-
...6-support-documents.jpg => 06-support.jpg} | Bin
boards/beaglebone/ai-64/update.rst | 60 -
18 files changed, 4400 insertions(+), 4381 deletions(-)
create mode 100644 boards/beaglebone/ai-64/01-introduction.rst
rename boards/beaglebone/ai-64/{ch03.rst => 02-quick-start.rst} (70%)
create mode 100644 boards/beaglebone/ai-64/03-design-and-specifications.rst
rename boards/beaglebone/ai-64/{ch07.rst => 04-connectors-and-pinouts.rst} (99%)
create mode 100644 boards/beaglebone/ai-64/05-demos-and-tutorials.rst
create mode 100644 boards/beaglebone/ai-64/06-support.rst
delete mode 100644 boards/beaglebone/ai-64/ch01.rst
delete mode 100644 boards/beaglebone/ai-64/ch02.rst
delete mode 100644 boards/beaglebone/ai-64/ch04.rst
delete mode 100644 boards/beaglebone/ai-64/ch05.rst
delete mode 100644 boards/beaglebone/ai-64/ch06.rst
delete mode 100644 boards/beaglebone/ai-64/ch08.rst
delete mode 100644 boards/beaglebone/ai-64/ch09.rst
delete mode 100644 boards/beaglebone/ai-64/ch10.rst
delete mode 100644 boards/beaglebone/ai-64/ch11.rst
rename boards/beaglebone/ai-64/media/chapter-thumbnails/{06-support-documents.jpg => 06-support.jpg} (100%)
delete mode 100644 boards/beaglebone/ai-64/update.rst
diff --git a/boards/beaglebone/ai-64/01-introduction.rst b/boards/beaglebone/ai-64/01-introduction.rst
new file mode 100644
index 00000000..a7a24761
--- /dev/null
+++ b/boards/beaglebone/ai-64/01-introduction.rst
@@ -0,0 +1,168 @@
+.. _bbai64-introduction:
+
+Introduction
+###############
+
+BeagleBone AI-64 like its predecessors (BeagleBone AI), is designed to address the
+open-source Community, early adopters, and anyone interested in a low cost 64-bit
+Dual Arm® Cortex®-A72 processor based Single Board Computer (SBC). It also offers
+access to many of the interfaces and allows for the use of add-on boards called
+capes, to add many different combinations of features. A user may also develop
+their own board or add their own circuitry.
+
+.. note::
+ AI-64 has been equipped with a minimum set of features to allow the user to experience the power
+ of the processor and is not intended as a full development platform as many of the features and
+ interfaces supplied by the processor are not accessible from BeagleBone AI-64 via onboard support
+ of some interfaces. It is not a complete product designed to do any particular function. It is a
+ foundation for experimentation and learning how to program the processor and to access the
+ peripherals by the creation of your own software and hardware.
+
+
+
+.. _beaglebone-compatibility:
+
+BeagleBone Compatibility
+-------------------------
+
+The board is intended to provide functionality well beyond BeagleBone Black or BeagleBone AI,
+while still providing compatibility with BeagleBone Black's expansion headers as
+much as possible. There are several significant differences between the three designs.
+
+.. _beaglebone-comparison-table, BeagleBone Comparison:
+
+.. table:: Table: BeagleBone Compatibility
+
+ +-------------------+---------------------+----------------------------+--------------------+
+ | Feature | AI-64 | AI | Black |
+ +===================+=====================+============================+====================+
+ | SoC | TDA4VM | AM5729 | AM3358 |
+ +-------------------+---------------------+----------------------------+--------------------+
+ | Arm CPU | Cortex-A72 (64-bit) | Cortex-A15 (32-bit) | Cortex-A8 (32-bit) |
+ +-------------------+---------------------+----------------------------+--------------------+
+ | Arm cores/MHz | 2x 2GHz | 2x 1.5GHz | 1x 1GHz |
+ +-------------------+---------------------+----------------------------+--------------------+
+ | RAM | 4GB | 1GB | 512MB |
+ +-------------------+---------------------+----------------------------+--------------------+
+ | eMMC flash | 16GB | 16GB | 4GB |
+ +-------------------+---------------------+----------------------------+--------------------+
+ | Size | 4" x 3.1" | 3.4" x 2.1" | .4" x 2.1" |
+ +-------------------+---------------------+----------------------------+--------------------+
+ | Display | miniDP + DSI | microHDMI | microHDMI |
+ +-------------------+---------------------+----------------------------+--------------------+
+ | USB host (Type-A) | 2x 5Gbps | 1x 480Mbps | 1x 480Mbps |
+ +-------------------+---------------------+----------------------------+--------------------+
+ | USB dual-role | Type-C 5Gbps | Type-C 5Gbps | mini-AB 480Mbps |
+ +-------------------+---------------------+----------------------------+--------------------+
+ | Ethernet | 10/100/1000M | 10/100/1000M | 10/100M |
+ +-------------------+---------------------+----------------------------+--------------------+
+ | M.2 | E-key | `-` | `-` |
+ +-------------------+---------------------+----------------------------+--------------------+
+ | WiFi/ Bluetooth | `-` | AzureWave AW‑CM256SM | `-` |
+ +-------------------+---------------------+----------------------------+--------------------+
+
+
+.. todo::
+
+ add cape compatibility details
+
+
+.. _beaglebone-ai-64-features-and-specificationd:
+
+BeagleBone AI-64 Features and Specification
+---------------------------------------------
+
+This section covers the specifications and features of the board and provides a high level
+description of the major components and interfaces that make up the board.
+
+.. _ai64-features,BeagleBone AI-64 features tabled:
+
+.. table:: Table: BeagleBone AI-64 Features and Specification
+
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | | Feature |
+ +=========================+=========================================================================================================================================+
+ | **Processor** | Texas Instruments TDA4VM |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **Graphics Engine** | PowerVR® Series8XE GE8430 |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **SDRAM Memory** | LPDDR4 3.2GHz (4GB) Kingston Q3222PM1WDGTK-U |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **Onboard Flash** | eMMC (16GB) Kingston EMMC16G-TB29-PZ90 |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **PMIC** | TPS65941213 and TPS65941111 PMICs regulator and one additional LDO. |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **Debug Support** | 2x 3 pin 3.3V TTL header |
+ | | 1. WKUP_UART0: Wake-up domain serial port |
+ | | 2. UART0: Main domain serial port |
+ | | 10-pin JTAG TAG-CONNECT footprint |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **Power Source** | USB C or DC Jack (5V @ >3A) |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **PCB** | 4†x 3.1†|
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **Indicators** | 1x Power & 5x User Controllable LEDs |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **USB-3.0 Client Port** | Access to USB0 SuperSpeed dual-role mode via USB-C (no power output) |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **USB-3.0 Host Port** | TUSB8041 4-port SuperSpeed hub 1x on USB1, 2x Type A Socket up-to 2.8A total depending on power input |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **Ethernet** | Gigabit RJ45 link indicator speed indicator |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **SD/MMC Connector** | microSD (1.8/3.3V) |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **User Input** | 1. Reset Button |
+ | | 2. Boot Button |
+ | | 3. Power Button |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **Video Out** | miniDP |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **Audio** | via miniDP (stereo) |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **Weight** | 192gm (with heatsink) |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+ | **Power** | Refer to :ref:`main-board-power` section |
+ +-------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+
+
+
+.. _board-component-locations:
+
+Board Component Locations
+----------------------------
+
+This section describes the key components on the board. It provides information on their location
+and function. Familiarize yourself with the various components on the board.
+
+.. _board-components:
+
+Board components
+-----------------
+
+:ref:`board-components-figure` below shows the locations of the connectors, LEDs, and switches on the PCB layout of the board.
+
+.. _board-components-figure:
+
+.. figure:: media/ch04/components.*
+ :width: 400px
+ :align: center
+
+ BeagleBone AI-64 board components
+
+* **DC Power** is the main DC input that accepts 5V power.
+* **Power Button** alerts the processor to initiate the power down sequence and is used to power down the board.
+* **GigaBit Ethernet** is the connection to the LAN.
+* **Serial Debug ports** WKUP_UART0 for early boot from the management MCU and UART0 is for the main processor.
+* **USB Client** is a USB-C connection to a PC that can also power the board.
+* **BOOT switch** can be used to force a boot from the microSD card if the power is cycled on the board, removing power and reapplying the power to the board.
+* There are five green **LEDs** that can be used by the user.
+* **Reset Button** allows the user to reset the processor.
+* **microSD** slot is where a microSD card can be installed.
+* **miniDP** connector is where the display is connected to.
+* **USB Host** can be connected different USB interfaces such as Wi-Fi, Bluetooth, Keyboard, etc.
+
+On bottom side we have,
+
+* **TI TDA4VM** processor.
+* **4GB LPDDR4** Dual Data Rate RAM memory.
+* **Ethernet PHY** physical interface to the network.
+* **eMMC** onboard MMC chip that holds up to 16GB of data.
diff --git a/boards/beaglebone/ai-64/ch03.rst b/boards/beaglebone/ai-64/02-quick-start.rst
similarity index 70%
rename from boards/beaglebone/ai-64/ch03.rst
rename to boards/beaglebone/ai-64/02-quick-start.rst
index d8c3c7cd..12be80ce 100644
--- a/boards/beaglebone/ai-64/ch03.rst
+++ b/boards/beaglebone/ai-64/02-quick-start.rst
@@ -3,7 +3,8 @@
Connecting up your BeagleBone AI-64
#####################################
-This section provides instructions on how to hook up your board. This beagle requires a 5V > 3A power supply to work properly via either USB Type-C power adapter or a barrel jack power adapter.
+This section provides instructions on how to hook up your board. This beagle requires a 5V > 3A
+power supply to work properly via either USB Type-C power adapter or a barrel jack power adapter.
Recommended adapters:
@@ -17,10 +18,11 @@ All the :ref:`BeagleBone AI-64 connections ports` we will use in this chapter ar
.. figure:: media/ch03/ports.*
:width: 400px
:align: center
- :caption: BeagleBone AI-64 connections ports
+
+ BeagleBone AI-64 connections ports
Methods of operation
-----------------------
+---------------------
1. Tethered to a PC
2. Standalone development platform in a PC configuration using external peripherals
@@ -28,30 +30,32 @@ Methods of operation
.. _whats-in-the-box:
What’s In the Box
----------------------------
+-------------------
In the box you will find three main items as shown in :ref:`bbai-64-pacakage`.
* BeagleBone AI-64.
* Instruction card.
-A USB-C to USB-C cable is not included bot recommended for the tethered scenario and creates an out of box experience where the board can be used immediately with no other equipment needed.
+A USB-C to USB-C cable is not included bot recommended for the tethered scenario and creates
+an out of box experience where the board can be used immediately with no other equipment needed.
.. _bbai-64-pacakage:
.. figure:: media/ch03/bbai64-in-box.*
:width: 400px
:align: center
- :caption: BeagleBone AI-64 box content
+
+ BeagleBone AI-64 box content
.. _main-connection-scenarios:
Main Connection Scenarios
--------------------------------
-
-This section describes how to connect and power the board and serves as a slightly more detailed description of the Quick Start Guide included in the box.
+--------------------------
-The board can be configured in several different ways, but we will discuss the two most common scenarios.
+This section describes how to connect and power the board and serves as a slightly more detailed
+description of the Quick Start Guide included in the box. The board can be configured in several
+different ways, but we will discuss the two most common scenarios.
* Tethered to a PC via the USB cable
@@ -68,7 +72,7 @@ Each of these configurations is discussed in general terms in the following sect
.. _tethered-to-a-pc:
Tethered To A PC
--------------------------
+-----------------
In this configuration, the board is powered by the PC via a single USB cable. The board is accessed either as a USB storage drive or via the browser on the connected PC. You need to use either Firefox or Chrome on the PC, Internet Explorer will not work properly.
@@ -77,14 +81,19 @@ In this configuration, the board is powered by the PC via a single USB cable. Th
.. figure:: media/ch03/usb-tethering.*
:width: 400px
:align: center
- :caption: Tethered Configuration
+
+ Tethered Configuration
-At least 5V @ 3A is required to power the board, In most cases the PC may not be able to supply sufficient power for the board unless the connection is made over a Type-C to Type-C cable. You should always use an external 5V > 3A DC power supply connected to the barrel jack if you are unsure that the system can provide the required power or are otherwise using a USB-A to Type-C cable which will always require power from the DC barrel jack.
+At least 5V @ 3A is required to power the board, In most cases the PC may not be able to supply
+sufficient power for the board unless the connection is made over a Type-C to Type-C cable. You
+should always use an external 5V > 3A DC power supply connected to the barrel jack if you are
+unsure that the system can provide the required power or are otherwise using a USB-A to Type-C
+cable which will always require power from the DC barrel jack.
.. _connect-the-cable-to-the-board:
Connect the Cable to the Board
-*************************************
+*******************************
1. Connect the type C USB cable to the board as shown in :ref:`usb-c-connect-figure`. The connector is on the top side of the board near barrel jack.
@@ -93,7 +102,8 @@ Connect the Cable to the Board
.. figure:: media/ch03/usb-c-connection.*
:width: 400px
:align: center
- :caption: USB Connection to the Board
+
+ USB Connection to the Board
2. Connect the USB-A end of the cable to your PC or laptop USB port as shown in the :ref:`usb-a-connect-figure` below.
@@ -102,7 +112,8 @@ Connect the Cable to the Board
.. figure:: media/ch03/usb-a-connection.*
:width: 400px
:align: center
- :caption: USB Connection to the PC/Laptop
+
+ USB Connection to the PC/Laptop
3. The board will power on and the power LED will be on as shown in :ref:`power-led-figure` below.
@@ -111,7 +122,8 @@ Connect the Cable to the Board
.. figure:: media/ch03/power-led.*
:width: 400px
:align: center
- :caption: Board Power LED
+
+ Board Power LED
4. When the board starts to the booting process started by the process of applying power, the LEDs will come on in sequence as shown in :ref:`boot-status-figure` below. It will take a few seconds for the status LEDs to come on, so be patient. The LEDs will be flashing in an erratic manner as it begins to boot the Linux kernel.
@@ -120,12 +132,13 @@ Connect the Cable to the Board
.. figure:: media/ch03/led-pattern.*
:width: 400px
:align: center
- :caption: Board Boot Status
+
+ Board Boot Status
.. _accessing-the-board-as-a-storage-drive:
Accessing the Board as a Storage Drive
-***********************************************
+****************************************
The board will appear around a USB Storage drive on your PC after thekernel has booted, which will take a round 10 seconds. The kernel on the board needs to boot before the port gets enumerated. Once the board appears as a storage drive, do the following:
@@ -137,7 +150,7 @@ The board will appear around a USB Storage drive on your PC after thekernel has
.. _standalone-wdisplay-and-keyboardmouse:
Standalone w/Display and Keyboard/Mouse
------------------------------------------------
+----------------------------------------
In this configuration, the board works more like a PC, totally free from any connection to a PC as shown in :ref:`desktop-config-figure`. It allows you to create your code to make the board do whatever you need it to do. It will however require certain common PC accessories. These accessories and instructions are described in the following section.
@@ -146,14 +159,15 @@ In this configuration, the board works more like a PC, totally free from any con
.. figure:: media/ch03/desktop-configuration.*
:width: 400px
:align: center
- :caption: Desktop Configuration
+
+ Desktop Configuration
Ethernet cable and M.2 WiFi + Bluetooth card are optional. They can be used if network access required.
.. _required-accessories:
Required Accessories
-***************************
+*********************
In order to use the board in this configuration, you will need the following accessories:
@@ -167,7 +181,7 @@ In order to use the board in this configuration, you will need the following acc
.. _connecting-up-the-board:
Connecting Up the Board
-******************************
+*************************
1. Connect the miniDP to DP or active miniDP to HDMI cable from your BeagleBone AI-64 to your monitor.
@@ -176,7 +190,8 @@ Connecting Up the Board
.. figure:: media/ch03/monitor-cable.*
:width: 400px
:align: center
- :caption: Connect miniDP-DP or active miniDP-HDMI cable to BeagleBone AI-64
+
+ Connect miniDP-DP or active miniDP-HDMI cable to BeagleBone AI-64
2. If you have an Display Port or HDMI monitor with HDMI-HDMI or DP-DP cable you can use adapters as shown in. :ref:`display-adapters-figure`.
@@ -185,11 +200,10 @@ Connecting Up the Board
.. figure:: media/ch03/display-adapters.*
:width: 400px
:align: center
- :caption: Display adapters
-
-3. If you have wired/wireless USB keyboard and mouse such as
- seen in :ref:`keyboard-mouse-figure` below, you need to plug the receiver in the USB host port of the board as shown in :ref:`keyboard-mouse-figure`.
+ Display adapters
+
+3. If you have wired/wireless USB keyboard and mouse such as seen in :ref:`keyboard-mouse-figure` below, you need to plug the receiver in the USB host port of the board as shown in :ref:`keyboard-mouse-figure`.
.. _keyboard-mouse-figure:
@@ -197,18 +211,22 @@ Connecting Up the Board
.. figure:: media/ch03/mouse-keyboard.*
:width: 400px
:align: center
- :caption: Keyboard and Mouse
+
+ Keyboard and Mouse
4. Connect the Ethernet Cable
-If you decide you want to connect to your local area network, an Ethernet cable can be used. Connect the Ethernet Cable to the Ethernet port as shown in :ref:`ethernet-cable-figure`. Any standard 100M Ethernet cable should work.
+If you decide you want to connect to your local area network, an Ethernet cable can be used.
+Connect the Ethernet Cable to the Ethernet port as shown in :ref:`ethernet-cable-figure`. Any
+standard 100M Ethernet cable should work.
.. _ethernet-cable-figure:
.. figure:: media/ch03/ethernet-cable.*
:width: 400px
:align: center
- :caption: Ethernet Cable Connection
+
+ Ethernet Cable Connection
5. The final step is to plug in the DC power supply to the DC power jack as shown in :ref:`barrel-jack-figure` below.
@@ -218,7 +236,8 @@ If you decide you want to connect to your local area network, an Ethernet cable
.. figure:: media/ch03/barrel-jack.*
:width: 400px
:align: center
- :caption: External DC Power
+
+ External DC Power
6. The cable needed to connect to your display is a miniDP-DP or active miniDP-HDMI. Connect the miniDP connector end to the board at this time. The connector is on the top side of the board as shown in :ref:`miniDP-figure` below.
@@ -227,7 +246,8 @@ If you decide you want to connect to your local area network, an Ethernet cable
.. figure:: media/ch03/miniDP-connector.*
:width: 400px
:align: center
- :caption: Connect miniDP to DP or active miniDP to HDMI Cable to the Board
+
+ Connect miniDP to DP or active miniDP to HDMI Cable to the Board
The connector is fairly robust, but we suggest that you not use the cable as a leash for your Beagle. Take proper care not to put too much stress on the connector or cable.
@@ -240,9 +260,11 @@ As soon as the power is applied to the board, it will start the booting up proce
.. figure:: media/ch03/leds.*
:width: 400px
:align: center
- :caption: BeagleBone AI-64 LEDs
+
+ BeagleBone AI-64 LEDs
-While the four user LEDS can be over written and used as desired, they do have specific meanings in the image that is shipped with the board once the Linux kernel has booted.
+While the four user LEDS can be over written and used as desired, they do have specific
+meanings in the image that is shipped with the board once the Linux kernel has booted.
* **USR0** is the heartbeat indicator from the Linux kernel.
* **USR1** turns on when the microSD card is being accessed
@@ -262,5 +284,67 @@ While the four user LEDS can be over written and used as desired, they do have s
.. figure:: media/ch03/xfce-desktop.*
:width: 400px
:align: center
- :caption: BeagleBone XFCE Desktop Screen
+
+ BeagleBone XFCE Desktop Screen
+
+.. _bbai64-update:
+
+Update software on BeagleBone AI-64
+###################################
+
+Production boards currently ship with the factory-installed 2022-01-14-8GB image. To upgrade
+from the software image on your BeagleBone AI-64 to the latest, you don't need to completely
+reflash the board. If you do want to reflash it, visit the flashing instructions on the getting
+started page. Factory Image update (without reflashing)…
+
+.. code-block:: bash
+ :linenos:
+
+ sudo apt update
+ sudo apt install --only-upgrade bb-j721e-evm-firmware generic-sys-mods
+ sudo apt upgrade
+
+Update U-Boot:
+==============
+
+to ensure only tiboot3.bin is in boot0, the pre-production image we tried to do more in boot0, but failed…
+
+.. code-block:: bash
+ :linenos:
+
+ sudo /opt/u-boot/bb-u-boot-beagleboneai64/install-emmc.sh
+ sudo /opt/u-boot/bb-u-boot-beagleboneai64/install-microsd.sh
+ sudo reboot
+
+Update Kernel and SGX modules:
+==============================
+
+.. code-block:: bash
+ :linenos:
+
+ sudo apt install bbb.io-kernel-5.10-ti-k3-j721e
+
+Update xfce:
+============
+
+.. code-block:: bash
+ :linenos:
+
+ sudo apt install bbb.io-xfce4-desktop
+
+Update ti-edge-ai 8.2 examples
+==============================
+
+.. code-block:: bash
+ :linenos:
+
+ sudo apt install ti-edgeai-8.2-base ti-vision-apps-8.2 ti-vision-apps-eaik-firmware-8.2
+
+Cleanup:
+========
+
+.. code-block:: bash
+ :linenos:
+
+ sudo apt autoremove --purge
diff --git a/boards/beaglebone/ai-64/03-design-and-specifications.rst b/boards/beaglebone/ai-64/03-design-and-specifications.rst
new file mode 100644
index 00000000..6771cdb4
--- /dev/null
+++ b/boards/beaglebone/ai-64/03-design-and-specifications.rst
@@ -0,0 +1,3893 @@
+.. _beaglebone-ai-64-high-level-specification:
+
+BeagleBone AI-64 High Level Specification
+##############################################
+
+:ref:`BeagleBone_AI-64-block-diagram` below shows the high level block
+diagram of BeagleBone AI-64 board surrounding TDA4VM SoC.
+
+.. _BeagleBone_AI-64-block-diagram:
+
+.. figure:: media/ch05/board-block-diagram.*
+ :width: 400px
+ :align: center
+
+ BeagleBone AI-64 Key Components
+
+.. _processor:
+
+Processor
+----------
+
+BeagleBone AI-64 uses TI J721E-family `TDA4VM <https://www.ti.com/product/TDA4VM>`_
+system-on-chip (SoC) which is part of the K3 Multicore SoC architecture platform
+and it is targeted for the reliability and low-latency needs of the automotive
+market provide for a great general purpose platform suitable for industrial
+automation, mobile robotics, building automation and numerous hobby projects.
+
+The SoC designed as a low power, high performance and highly integrated device
+architecture, adding significant enhancement on processing power, graphics capability,
+video and imaging processing, virtualization and coherent memory support. In addition,
+these SoCs support state of the art security and functional safety features. For the
+remaining of this section device, SoC, and processor will be used interchangeably.
+
+**Some of the main distinguished characteristics of the device are:**
+
+* 64-bit architecture with virtualization and coherent memory support, which leverages full processing capability of 64-bit Arm® Cortex®-A72
+* Fully programmable industrial communication subsystems to enable future-proof designs for customers that need to adopt the new Gigabit Time-sensitive Networks (TSN) standards, but still need full support on legacy protocols and continuous system optimization over the product deployment
+* Integration of vision hardware processing accelerators to facilitate extensive processing requirements in low power budget for automotive ADAS and machine vision applications
+* Integration of a general-purpose microcontroller unit (MCU) with a dual Arm® Cortex®-R5F MCU subsystem, available for general purpose use as two cores or in lockstep, intended to help customers achieve functional safety goals for their end products
+* Integration of a next-generation fixed and floating-point C71x Digital Signal Processor (DSP) that significantly boosts power over a broad range of general signal processing tasks for both general applications and automotive functions which also incorporates advanced techniques to improve control code efficiency and ease of programming such as branch prediction, protected pipeline, precise exception and virtual memory management
+* Tightly coupled Matrix Multiplication Accelerator (MMA) that extends the C71x DSP architecture's scalar and vector facilities enabling deep learning and enhance vision, analytics and wide range of general applications. The achieved total TOPS (Tera Operations Per Second) performance significantly differentiates the device for single board computer in machine vision and deep learning applications
+* Key display features including flexibility to interface with different panel types (eDP, DSI, DPI) with multi-layer hardware composition
+* Integration of hardware features that help applications to achieve functional safety mechanisms
+* Robust security architecture with sandboxed DMSC controller managing all secure configurations with high performance client-server messaging scheme between secure DMSC and all cores
+* Simplified solution for power supply management, enabling lower cost system solution (on-die bias LDOs and power good comparators for minimal power sequencing requirements consistent with low cost supply design)
+
+**The device is composed of the following main subsystems, across different domains of the SoC, among others:**
+
+* One dual-core 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz and up to 24K DMIPS (Dhrystone Million Instructions per Second)
+* Up to three Microcontroller Units (MCU), based on dual-core Arm Cortex-R5F processor running at up to 1.0 GHz, up to 12K DMIPS
+* Up to two TMS320C66x DSP CorePac modules running at up to 1.35 GHz, up to 40 GFLOPS
+* One C71x floating point, vector DSP running at up to 1.0 GHz, up to 80 GFLOPS
+* One deep-learning MMA, up to 8 TOPS (8b) at 1.0 GHz
+* Up to two gigabit dual-core Programmable Real-Time Unit and Industrial Communication Subsystems (PRU_ICSSG)
+* Two Navigator Subsystems (NAVSS) for data movement and control
+* One multi-pipeline Display Subsystem (DSS) with one MIPI® Display Serial Interface Controller (DSI) and shared MIPI D-PHY Transmitter (DPHY_TX), one Embedded DisplayPort Transmitter (EDP) with shared Serializer/Deserializer (SERDES), and two MIPI Display Pixel Interface (DPI) ports
+* Two Camera Streaming Interface Receivers (CSI_RX_IF) with dedicated MIPI D-PHYs (DPHY_RX)
+* One Camera Streaming Interface Transmitter (CSI_TX_IF) with MIPI D-PHY Transmitter (DPHY_TX) shared with DSI
+* One Vision Processing Accelerator (VPAC) with image signal processor
+* One Depth and Motion Processing Accelerator (DMPAC)
+* One dual-core multi-standard HD Video Decoder (DECODER)
+* One dual-core multi-standard HD Video Encoder (ENCODER)
+* One Graphics Processing Unit (GPU)
+* One Device Management and Security Controller (DMSC)
+
+**The device provides a rich set of peripherals such as:**
+
+* General connectivity peripherals, including:
+
+ * ``Two 12-bit general purpose Analog-to-Digital Converters (ADC)``
+ * ``Ten Inter-Integrated Circuit (I2C) interfaces``
+ * ``Three Improved Inter-Integrated Circuit (I3C) controllers``
+ * ``Eleven master/slave Multichannel Serial Peripheral Interfaces (MCSPI)``
+ * ``Twelve configurable Universal Asynchronous Receiver/Transmitter (UART) interfaces``
+ * ``Ten General-Purpose Input/Output (GPIO) modules``
+
+* High-speed interfaces, including:
+
+ * ``Two Gigabit Ethernet Switch (CPSW) modules``
+ * ``Two Dual-Role-Device (DRD) Universal Serial Bus Subsystems (USBSS) with integrated PHY``
+ * ``Four Peripheral Component Interconnect express (PCIe) Gen3 subsystems``
+
+* Flash memory interfaces, including:
+
+ * ``One Octal SPI (OSPI) interface and one Quad SPI (QSPI) or one QSPI and one HyperBus^TM^``
+ * ``One General Purpose Memory Controller (GPMC) with Error Location Module (ELM) and 8- or 16-bit-wide data bus width (supports parallel NOR or NAND FLASH devices)``
+ * ``Three Multimedia Card/Secure Digital (MMCSD) controllers``
+ * ``One Universal Flash Storage (UFS) interface``
+
+* Industrial and control interfaces, including:
+
+ * ``Sixteen Controller Area Network (MCAN) interfaces with flexible data rate support``
+ * ``Three Enhanced Capture (ECAP) modules``
+ * ``Six Enhanced Pulse-Width Modulation (EPWM) subsystems``
+ * ``Three Enhanced Quadrature Encoder Pulse (EQEP) modules``
+
+* Audio peripherals, including:
+
+ * ``One Audio Tracking Logic (ATL)``
+ * ``Twelve Multichannel Audio Serial Port (MCASP) modules supporting up to 16 channels with independent TX/RX clock/sync domain``
+
+* One Video Processing Front End (VPFE) interface module
+
+**The device also integrates:**
+
+* Power distribution, reset controls and clock management components
+
+* Power-management techniques for device power consumption minimization:
+
+ * ``Adaptive Voltage Scaling (AVS)``
+ * ``Dynamic Frequency Scaling (DFS)``
+ * ``Gated clocks``
+ * ``Multiple voltage domains``
+ * ``Independently controlled power domains for major modules``
+ * ``Voltage and Temperature Management (VTM) module``
+ * ``Power-on Reset Generators (PRG)``
+ * ``Power Sleep Controllers (PSC)``
+
+* Optimized interconnect (CBASS) architecture to enable latency-critical real time network and IO applications
+
+* Control modules (CTRL_MMRs) mainly associated with device top-level configurations such as:
+
+ * ``IO Pad and pin multiplexing configuration``
+ * ``PLL control and associated High-Speed Dividers (HSDIV)``
+ * ``Clock selection``
+ * ``Analog function controls``
+
+* Multicore Shared Memory Controller (MSMC)
+* DDR Subsystem (DDRSS) with Error Correcting Code (ECC), supporting LPDDR4
+* 1KB RAM with ECC support for C71x boot vectors
+* 2KB RAM with ECC support for A72 and R5F boot vectors
+* 512KB On-Chip SRAM protected by ECC
+* One Global Time Counter (GTC) module
+* Thirty 32-bit counter timers with compare and capture modes
+* Debug and trace capabilities
+
+**The device includes different modules for functional safety requirements support:**
+
+* MCU island with dual lock step Arm Cortex-R5F
+* Safety enabled interconnect with implemented features to help with Freedom From Interference (FFI)
+* Twelve Real Time Interrupt (RTI) modules with Windowed Watchdog Timer (WWDT) functionality to monitor processor cores
+* Sixteen Dual-Clock Comparators (DCC) to monitor clocking sources during run-time
+* Three Error Signaling Modules (ESM) to enable error monitoring
+* Temperature monitoring sensors
+* ECC on all critical memories
+* Dedicated hardware Memory Cyclic Redundancy Check (MCRC) blocks
+
+**The device supports the following main security functionalities among others:**
+
+* Secure Boot Management
+* Public Key Accelerator (PKA) for large vector math operation
+* Cryptographic acceleration (AES, 3DES, MD5, SHA1, SHA2-224, 256, 512 operation)
+* Trusted Execution Environment (TEE)
+* Secure storage support
+* On-the-fly encryption and authentication support for OSPI interface
+
+The device is partitioned into three functional domains as shown in :ref:`soc-block-diagram`, each containing specific processing cores and peripherals:
+
+* Wake-up (WKUP) domain
+* Microcontroller (MCU) domain with one of the dual Cortex-R5 cluster
+* MAIN domain
+
+.. _soc-block-diagram:
+
+.. figure:: media/ch05/soc-block-diagram.*
+ :width: 400px
+ :align: center
+
+ Device Top-level Block Diagram
+
+.. _memory:
+
+Memory
+-------
+
+Described in the following sections are the three memory devices found on the board.
+
+.. _mb-ddr4l:
+
+4GB LPDDR4
+************
+
+A single (1024M x 16bits x 2channels) LPDDR4 4Gb memory device is used. The memory used is:
+
+* Kingston Q3222PM1WDGTK-U
+
+.. _kb-eeprom:
+
+4Kb EEPROM
+*************
+
+A single 4Kb EEPROM (24FC04HT-I/OT) is provided on I2C0 that holds the board information. This information includes board name, serial number, and revision information.
+
+.. _gb-embedded-mmc:
+
+16GB Embedded MMC
+*******************
+
+A single 16GB embedded MMC (eMMC) device is on the board. The device
+connects to the MMC1 port of the processor, allowing for 8bit wide
+access. Default boot mode for the board will be MMC1 with an option to
+change it to MMC0, the SD card slot, for booting from the SD card as a
+result of removing and reapplying the power to the board. Simply
+pressing the reset button will not change the boot mode. MMC0 cannot be
+used in 8Bit mode because the lower data pins are located on the pins
+used by the Ethernet port. This does not interfere with SD card
+operation but it does make it unsuitable for use as an eMMC port if the
+8 bit feature is needed.
+
+.. _microsd-connector:
+
+MicroSD Connector
+*******************
+
+The board is equipped with a single microSD connector to act as the
+secondary boot source for the board and, if selected as such, can be the
+primary boot source. The connector will support larger capacity microSD
+cards. The microSD card is not provided with the board. Booting from
+MMC0 will be used to flash the eMMC in the production environment or can
+be used by the user to update the SW as needed.
+
+.. _boot-modes:
+
+Boot Modes
+***********
+
+As mentioned earlier, there are two boot modes:
+
+* **eMMC Boot:** This is the default boot mode and will allow for the fastest boot time and will enable the board to boot out of the box using the pre-flashed OS image without having to purchase an microSD card or an microSD card writer.
+* **SD Boot:** This mode will boot from the microSD slot. This mode can be used to override what is on the eMMC device and can be used to program the eMMC when used in the manufacturing process or for field updates.
+
+.. todo::
+
+ This section needs more work and references to greater detail. Other boot modes are possible.
+ Software to support USB and serial boot modes is not provided by beagleboard.org._Please contact TI for support of this feature.
+
+
+A switch is provided to allow switching between the modes.
+
+* Holding the boot switch down during a removal and reapplication of power without a microSD card inserted will force the boot source to be the USB port and if nothing is detected on the USB client port, it will go to the serial port for download.
+* Without holding the switch, the board will boot try to boot from the eMMC. If it is empty, then it will try booting from the microSD slot, followed by the serial port, and then the USB port.
+* If you hold the boot switch down during the removal and reapplication of power to the board, and you have a microSD card inserted with a bootable image, the board will boot from the microSD card.
+
+.. note ::
+
+ Pressing the RESET button on the board will NOT result in a change of the boot mode. You MUST remove power and reapply power to change the boot mode. The boot pins are sampled during power on reset from the PMIC to the processor.The reset button on the board is a warm reset only and will not force a boot mode change.
+
+.. _power-management:
+
+Power Management
+-------------------
+
+The *TPS65941213 and TPS65941111* power management device is used along with a separate LDO to provide power to the system.
+
+.. _pc-usb-interface:
+
+PC USB Interface
+---------------------
+
+The board has a USB type-C connector that connects to USB0 port of the processor.
+
+.. _serial-debug-ports:
+
+Serial Debug Ports
+------------------------------------
+
+Two serial debug ports are provided on board via 3pin micro headers,
+
+1. WKUP_UART0: Wake-up domain serial port
+2. UART0: Main domain serial port
+
+
+In order to use the interfaces a `3pin micro to 6pin dupont adaptor header <https://uk.farnell.com/element14/1103004000156/beaglebone-ai-serials-cable/dp/3291081>`_ is required with a 6 pin USB to TTL adapter. The header is compatible with the one provided by FTDI and can be purchased for about $$12 to $$20 from various sources. Signals supported are TX and RX. None of the handshake signals are supported.
+
+.. _usb1-host-port:
+
+USB1 Host Port
+------------------
+
+On the board is a single USB Type A female connector with full LS/FS/HS
+Host support that connects to USB1 on the processor. The port can
+provide power on/off control and up to 1.5A of current at 5V. Under USB
+power, the board will not be able to supply the full 1.5A, but should
+be sufficient to supply enough current for a lower power USB device
+supplying power between 50 to 100mA.
+
+.. _power-sources:
+
+Power Sources
+------------------------------------
+
+The board can be powered from two different sources:
+
+* A 5V > 3A power supply plugged into the barrel jack.
+* A wall adaptor with 5V > 3A output power.
+
+The power supply is not provided with the board but can be easily
+obtained from numerous sources. A 5V > 3A supply is mandatory to have with
+the board, but if there is a cape plugged into the board or you have a power
+hungry device or hub plugged into the host port, then more current may
+needed from the DC supply.
+
+.. _reset-button:
+
+Reset Button
+------------------------------------
+
+When pressed and released, causes a reset of the board.
+
+.. _power-button:
+
+Power Button
+------------------------------------
+
+This button takes advantage of the input to the PMIC for
+power down features.
+
+.. _indicators:
+
+Indicators
+------------------------------------
+
+There are a total of six green LEDs on the board.
+
+* One green power LED indicates that power is applied and the power management IC is up.
+* Five blue LEDs that can be controlled via the SW by setting GPIO pins.
+
+:orphan:
+
+.. _bbai64-detailed-hardware-design:
+
+Detailed Hardware Design
+#########################
+
+This section provides a detailed description of the Hardware design.
+This can be useful for interfacing, writing drivers, or using it to help
+modify specifics of your own design.
+
+:ref:`bbai-64-block-diagram-ch06` below is the high level block diagram of the board. For those who may be concerned, It is the same figure as shown in :ref:`beaglebone-ai-64-high-level-specification`. It is placed here again for convenience so it is closer to the topics to follow.
+
+.. _bbai-64-block-diagram-ch06:
+
+.. figure:: media/ch05/board-block-diagram.*
+ :width: 400px
+ :align: center
+ :alt: BeagleBone AI-64 Key Components
+
+ BeagleBone AI-64 Key Components
+
+.. _power-section:
+
+Power Section
+--------------
+
+:ref:`power-flow-diagram` shows the high level block diagram of the power section of the board.
+
+.. _power-flow-diagram,High level power block diagram:
+
+.. figure:: media/ch06/power.*
+ :width: 400px
+ :align: center
+ :alt: Fig: High level power block diagram
+
+ Fig: High level power block diagram
+
+This section describes the power section of the design and all the
+functions performed by the *TPS65941213 and TPS65941111*.
+
+.. todo::
+
+ The above image does not represent this board. It has a Pi Header.
+
+.. _TPS65941213-and-TPS65941111-pmic:
+
+TPS65941213 and TPS65941111 PMIC
+**********************************
+
+The main Power Management IC (PMIC) in the system is the *TPS65941213 and TPS65941111* which is a
+single chip power management IC consisting of a linear dual-input power path, three step-down
+converters, and four LDOs. LDO stands for Low Drop Out. If you want to know more about an LDO, you can
+go to `http://en.wikipedia.org/wiki/Low-dropout_regulator <http://en.wikipedia.org/wiki/Low-dropout_regulator>`_ .
+
+If you want to learn more about step-down converters, you can go to
+`_http://en.wikipedia.org/wiki/DC-to-DC_converter <http://en.wikipedia.org/wiki/DC-to-DC_converter>`_.
+
+The system is supplied by a USB port or DC adapter. Three
+high-efficiency 2.25MHz step-down converters are targeted at providing
+the core voltage, MPU, and memory voltage for the board.
+
+The step-down converters enter a low power mode at light load for
+maximum efficiency across the widest possible range of load currents.
+For low-noise applications the devices can be forced into fixed
+frequency PWM using the I2C interface. The step-down converters allow
+the use of small inductors and capacitors to achieve a small footprint
+solution size.
+
+LDO1 and LDO2 are intended to support system standby mode. In normal
+operation, they can support up to 100mA each. LDO3 and LDO4 can support
+up to 285mA each.
+
+By default only LDO1 is always ON but any rail can be configured to
+remain up in SLEEP state. In particular the DCDC converters can remain
+up in a low-power PFM mode to support processor suspend mode. The
+*TPS65941213 and TPS65941111* offers flexible power-up and power-down sequencing and
+several house-keeping functions such as power-good output, pushbutton
+monitor, hardware reset function and temperature sensor to protect the
+battery.
+
+See the :ref:`TPS6594-Q1-block-diagram` shown below for high level details
+for *TPS65941213 and TPS65941111*, for more information on the, refer to https://www.ti.com/product/TPS6594-Q1 Texas instruments product page.
+
+.. _TPS6594-Q1-block-diagram:
+
+.. figure:: images/ch06/TPS6594-Q1.*
+ :width: 400px
+ :align: center
+ :alt: TPS6594-Q1 block diagram
+
+ TPS6594-Q1 block diagram
+
+.. _pmic-a-diagram,PMIC-A TPS65941213 circuit:
+
+.. figure:: images/ch06/pmic-a.*
+ :width: 400px
+ :align: center
+ :alt: PMIC-B TPS65941213 circuit
+
+ PMIC-B TPS65941213 circuit
+
+.. _pmic-b-diagram,PMIC-B TPS65941111 circuit:
+
+.. figure:: images/ch06/pmic-b.*
+ :width: 400px
+ :align: center
+ :alt: PMIC-B TPS65941111 circuit
+
+ PMIC-B TPS65941111 circuit
+
+.. _dc-input:
+
+DC Input
+***********
+
+:ref:`figure-23` below shows how the DC input is connected to the **TPS65941213 and TPS65941111**.
+
+.. _figure-23,Figure 23:
+
+.. figure:: media/image38.*
+ :width: 400px
+ :align: center
+ :alt: TPS65217 DC Connection
+
+ TPS65217 DC Connection
+
+A 5VDC supply can be used to provide power to the board. The power
+supply current depends on how many and what type of add-on boards are
+connected to the board. For typical use, a 5VDC supply rated at 1A
+should be sufficient. If heavier use of the expansion headers or USB
+host port is expected, then a higher current supply will be required.
+
+The connector used is a 2.1MM center positive x 5.5mm outer barrel. The
+5VDC rail is connected to the expansion header. It is possible to power
+the board via the expansion headers from an add-on card. The 5VDC is
+also available for use by the add-on cards when the power is supplied by
+the 5VDC jack on the board.
+
+.. _usb-power:
+
+USB Power
+*************
+
+The board can also be powered from the USB port. A typical USB 3.0 port is
+limited to 900mA. When powering from the USB port, the VDD_5V rail
+is not provided to the expansion headers, so capes that require the 5V
+rail to supply the cape direct, bypassing the *TPS65941213 and TPS65941111*, will not have
+that rail available for use. The 5VDC supply from the USB port is
+provided on the SYS_5V, the one that comes from the **TPS65941213 and TPS65941111**, rail
+of the expansion header for use by a cape. :ref:`bbai64-usb-power-connections` is the connection
+of the USB power input on the PMIC.
+
+.. _bbai64-usb-power-connections:
+
+.. figure:: media/USB-Connection.*
+ :width: 400px
+ :align: center
+
+ USB Power Connection
+
+.. _power-selection:
+
+Power Selection
+*****************
+
+The selection of either the 5VDC or the USB as the power source is
+handled internally to the *TPS65941213 and TPS65941111* and automatically switches to 5VDC
+power if both are connected. SW can change the power configuration via
+the I2C interface from the processor. In addition, the SW can read
+the *TPS65941213 and TPS65941111* and determine if the board is running on the 5VDC input
+or the USB input. This can be beneficial to know the capability of the
+board to supply current for things like operating frequency and
+expansion cards.
+
+It is possible to power the board from the USB input and then connect
+the DC power supply. The board will switch over automatically to the DC
+input.
+
+.. _power-button-1:
+
+Power Button
+**************
+
+A power button is connected to the input of the *TPS65941213 and TPS65941111*. This is a
+momentary switch, the same type of switch used for reset and boot
+selection on the board.
+
+If you push the button the *TPS65941213 and TPS65941111* will send an interrupt to the
+processor. It is up to the processor to then pull the **PMIC_POWER_EN**
+pin low at the correct time to power down the board. At this point, the
+PMIC is still active, assuming that the power input was not removed.
+Pressing the power button will cause the board to power up again if the
+processor puts the board in the power off mode.
+
+In power off mode, the RTC rail is still active, keeping the RTC powered
+and running off the main power input. If you remove that power, then the
+RTC will not be powered. You also have the option of using the battery
+holes on the board to connect a battery if desired as discussed in the
+next section.
+
+If you push and hold the button for greater than 8 seconds, the PMIC
+will power down. But you must release the button when the power LED
+turns off. Holding the button past that point will cause the board to
+power cycle.
+
+.. _section-6-1-7,Section 6.1.7 Power Consumption:
+
+Power Consumption
+*******************
+
+The power consumption of the board varies based on power scenarios and
+the board boot processes. Measurements were taken with the board in the
+following configuration:
+
+* DC powered and USB powered
+* monitor connected
+* USB HUB
+* 4GB USB flash drive
+* Ethernet connected @ 100M
+* Serial debug cable connected
+
+:ref:`table-4` is an analysis of the power consumption of the board in these various scenarios.
+
+.. _table-4,Table 4:
+
+.. list-table:: BeagleBone AI-64 Features and Specification
+ :header-rows: 1
+
+ * - MODE
+ - USB
+ - DC
+ - C+USB
+ * - Reset
+ - TBD
+ - TBD
+ - TBD
+ * - Idling @ UBoot
+ - 210
+ - 210
+ - 210
+ * - Kernel Booting (Peak)
+ - 460
+ - 460
+ - 460
+ * - Kernel Idling
+ - 350
+ - 350
+ - 350
+ * - Kernel Idling Display Blank
+ - 280
+ - 280
+ - 280
+ * - Loading a Webpage
+ - 430
+ - 430
+ - 430
+
+The current will fluctuate as various activates occur, such as the LEDs
+on and microSD/eMMC accesses.
+
+.. _processor-interfaces:
+
+Processor Interfaces
+**********************
+
+The processor interacts with the *TPS65941213 and TPS65941111* via several different
+signals. Each of these signals is described below.
+
+.. _bbai64-i2c0:
+
+I2C0
+*****
+
+I2C0 is the control interface between the processor and the *TPS65941213 and TPS65941111*.
+It allows the processor to control the registers inside the *TPS65941213 and TPS65941111*
+for such things as voltage scaling and switching of the input rails.
+
+.. _pmc_powr_en:
+
+PMIC_POWR_EN
+***************
+
+On power up the *VDD_RTC* rail activates first. After the RTC circuitry
+in the processor has activated it instructs the *TPS65941213 and TPS65941111* to initiate
+a full power up cycle by activating the *PMIC_POWR_EN* signal by taking
+it HI. When powering down, the processor can take this pin low to start
+the power down process.
+
+.. _ldo_good:
+
+LDO_GOOD
+*********
+
+This signal connects to the *RTC_PORZn* signal, RTC power on reset. The
+small “*n*†indicates that the signal is an active low signal. Word
+processors seem to be unable to put a bar over a word so the**n** is
+commonly used in electronics. As the RTC circuitry comes up first, this
+signal indicates that the LDOs, the 1.8V VRTC rail, is up and stable.
+This starts the power up process.
+
+.. _pmic_pgood:
+
+PMIC_PGOOD
+***********
+
+Once all the rails are up, the *PMIC_PGOOD* signal goes high. This
+releases the**PORZn** signal on the processor which was holding the
+processor reset.
+
+.. _wakeup:
+
+WAKEUP
+*******
+
+The WAKEUP signal from the *TPS65941213 and TPS65941111* is connected to the **EXT_WAKEUP**
+signal on the processor. This is used to wake up the processor when it
+is in a sleep mode. When an event is detected by the *TPS65941213 and TPS65941111*, such
+as the power button being pressed, it generates this signal.
+
+.. _pmic_int:
+
+PMIC_INT
+**********
+
+The *PMIC_INT* signal is an interrupt signal to the processor. Pressing
+the power button will send an interrupt to the processor allowing it to
+implement a power down mode in an orderly fashion, go into sleep mode,
+or cause it to wake up from a sleep mode. All of these require SW
+support.
+
+.. _power-rails:
+
+Power Rails
+*************
+
+:ref:`figure-25` shows the connections of each of the rails from the **TPS65941213 and TPS65941111**.
+
+.. _figure-25,Figure 25:
+
+.. figure:: media/image39.jpg
+ :width: 400px
+ :align: center
+
+ Power Rails
+
+VRTC Rail
+***********
+
+The *VRTC* rail is a 1.8V rail that is the first rail to come up in the power sequencing.
+It provides power to the RTC domain on the processor and the I/O rail of the **TPS65941213
+and TPS65941111**. It can deliver up to 250mA maximum.
+
+VDD_3V3A Rail
+**************
+
+The *VDD_3V3A* rail is supplied by the **TPS65941213 and TPS65941111** and provides the
+3.3V for the processor rails and can provide up to 400mA.
+
+VDD_3V3B Rail
+**************
+
+The current supplied by the *VDD_3V3A* rail is not sufficient to power
+all of the 3.3V rails on the board. So a second LDO is supplied, U4,
+a **TL5209A**, which sources the *VDD_3V3B* rail. It is powered up just
+after the *VDD_3V3A* rail.
+
+VDD_1V8 Rail
+**************
+
+The *VDD_1V8* rail can deliver up to 400mA and provides the power
+required for the 1.8V rails on the processor and the display framer. This
+rail is not accessible for use anywhere else on the board.
+
+VDD_CORE Rail
+***************
+
+The *VDD_CORE* rail can deliver up to 1.2A at 1.1V. This rail is not
+accessible for use anywhere else on the board and connects only to the
+processor. This rail is fixed at 1.1V and should not be adjusted by SW
+using the PMIC. If you do, then the processor will no longer work.
+
+VDD_MPU Rail
+**************
+
+The *VDD_MPU* rail can deliver up to 1.2A. This rail is not accessible
+for use anywhere else on the board and connects only to the processor.
+This rail defaults to 1.1V and can be scaled up to allow for higher
+frequency operation. Changing of the voltage is set via the I2C
+interface from the processor.
+
+VDDS_DDR Rail
+****************
+
+The *VDDS_DDR* rail defaults to**1.5V** to support the LPDDR4 rails and
+can deliver up to 1.2A. It is possible to adjust this voltage rail down
+to *1.35V* for lower power operation of the LPDDR4 device. Only LPDDR4
+devices can support this voltage setting of 1.35V.
+
+Power Sequencing
+******************
+
+The power up process is consists of several stages and events. :ref:`figure-26` describes the
+events that make up the power up process for the processer from the PMIC. This diagram is used
+elsewhere to convey additional information. I saw no need to bust it up into smaller diagrams.
+It is from the processor datasheet supplied by Texas Instruments.
+
+.. _figure-26,Figure 26:
+
+.. figure:: media/image40.*
+ :width: 400px
+ :align: center
+
+ Power Rail Power Up Sequencing
+
+:ref:`figure-27` the voltage rail sequencing for the**TPS65941213 and TPS65941111** as it
+powers up and the voltages on each rail. The power sequencing starts at
+15 and then goes to one. That is the way the *TPS65941213 and TPS65941111* is configured.
+You can refer to the TPS65941213 and TPS65941111 datasheet for more information.
+
+.. _figure-27,Figure 27:
+
+.. figure:: media/image41.*
+ :width: 400px
+ :align: center
+
+ TPS65941213 and TPS65941111 Power Sequencing Timing
+
+.. _power-led:
+
+Power LED
+***********
+
+The power LED is a blue LED that will turn on once the *TPS65941213 and TPS65941111* has
+finished the power up procedure. If you ever see the LED flash once,
+that means that the**TPS65941213 and TPS65941111** started the process and encountered an
+issue that caused it to shut down. The connection of the LED is shown in
+:ref:`figure-25`.
+
+.. _TPS65941213-and-TPS65941111-power-up-process:
+
+TPS65941213 and TPS65941111 Power Up Process
+*********************************************
+
+:ref:`figure-28` shows the interface between the **TPS65941213 and TPS65941111** and the processor.
+It is a cut from the PDF form of the schematic and reflects what is on the schematic.
+
+.. _figure-28,Figure 28:
+
+.. figure:: media/image42.jpg
+ :width: 400px
+ :align: center
+
+ Power Processor Interfaces
+
+When voltage is applied, DC or USB, the *TPS65941213 and TPS65941111* connects the power to the
+SYS output pin which drives the switchers and LDOs in the **TPS65941213 and TPS65941111**.
+
+At power up all switchers and LDOs are off except for the *VRTC LDO*
+(1.8V), which provides power to the VRTC rail and controls
+the **RTC_PORZn** input pin to the processor, which starts the power up
+process of the processor. Once the RTC rail powers up, the *RTC_PORZn*
+pin, driven by the *LDO_PGOOD* signal from the *TPS65941213 and TPS65941111*, of the
+processor is released.
+
+Once the *RTC_PORZn* reset is released, the processor starts the
+initialization process. After the RTC stabilizes, the processor launches
+the rest of the power up process by activating the**PMIC_POWER_EN**
+signal that is connected to the *TPS65941213 and TPS65941111* which starts the *TPS65941213 and TPS65941111*
+power up process.
+
+The *LDO_PGOOD* signal is provided by the**TPS65941213 and TPS65941111** to the processor.
+As this signal is 1.8V from the *TPS65941213 and TPS65941111* by virtue of the *TPS65941213 and TPS65941111*
+VIO rail being set to 1.8V, and the *RTC_PORZ* signal on the processor
+is 3.3V, a voltage level shifter, *U4*, is used. Once the LDOs and
+switchers are up on the *TPS65941213 and TPS65941111*, this signal goes active releasing
+the processor. The LDOs on the *TPS65941213 and TPS65941111* are used to power the VRTC
+rail on the processor.
+
+.. _processor-control-interface:
+
+Processor Control Interface
+*****************************
+
+:ref:`figure-28` above shows two interfaces between the processor and
+the **TPS65941213 and TPS65941111** used for control after the power up sequence has
+completed.
+
+The first is the *I2C0* bus. This allows the processor to turn on and
+off rails and to set the voltage levels of each regulator to supports
+such things as voltage scaling.
+
+The second is the interrupt signal. This allows the *TPS65941213 and TPS65941111* to alert
+the processor when there is an event, such as when the power button is
+pressed. The interrupt is an open drain output which makes it easy to
+interface to 3.3V of the processor.
+
+.. _low-power-mode-support:
+
+Low Power Mode Support
+**************************
+
+This section covers three general power down modes that are available.
+These modes are only described from a Hardware perspective as it relates
+to the HW design.
+
+RTC Only
+***********
+
+In this mode all rails are turned off except the *VDD_RTC*. The
+processor will need to turn off all the rails to enter this mode.
+The **VDD_RTC** staying on will keep the RTC active and provide for the
+wakeup interfaces to be active to respond to a wake up event.
+
+RTC Plus DDR
+****************
+
+In this mode all rails are turned off except the *VDD_RTC* and
+the **VDDS_DDR**, which powers the LPDDR4 memory. The processor will need
+to turn off all the rails to enter this mode. The *VDD_RTC* staying on
+will keep the RTC active and provide for the wakeup interfaces to be
+active to respond to a wake up event.
+
+The *VDDS_DDR* rail to the LPDDR4 is provided by the 1.5V rail of
+the **TPS65941213 and TPS65941111** and with *VDDS_DDR* active, the LPDDR4 can be placed in
+a self refresh mode by the processor prior to power down which allows
+the memory data to be saved.
+
+Currently, this feature is not included in the standard software
+release. The plan is to include it in future releases.
+
+Voltage Scaling
+****************
+
+For a mode where the lowest power is possible without going to sleep,
+this mode allows the voltage on the ARM processor to be lowered along
+with slowing the processor frequency down. The I2C0 bus is used to
+control the voltage scaling function in the *TPS65941213 and TPS65941111*.
+
+.. _sitara-am3358bzcz100-processor:
+
+TI J721E DRA829/TDA4VM/AM752x Processor
+-----------------------------------------
+
+The board is designed to use the TI J721E DRA829/TDA4VM/AM752x processor in the
+15 x 15 package.
+
+.. _description:
+
+Description
+*********************************************
+
+:ref:`figure-29` is a high level block diagram of the processor. For more information on the processor, go to `https://www.ti.com/product/TDA4VM <https://www.ti.com/product/TDA4VM>`_
+
+.. _figure-29,Figure 29:
+
+.. figure:: media/image43.*
+ :width: 400px
+ :align: center
+
+ Jacinto TDA4VMBZCZ Block Diagram
+
+
+.. _high-level-features:
+
+High Level Features
+*********************
+
+:ref:`table-5` below shows a few of the high level features of the Jacinto processor.
+
+.. _table-5,Table 5:
+
+.. list-table:: Table 5: Processor Features
+ :header-rows: 1
+
+ * - Operating Systems
+ - Linux, Android, Windows Embedded CE,QNX,ThreadX
+ - MMC/SD
+ - 3
+ * - Standby Power
+ - 7 mW
+ - CAN
+ - 2
+ * - ARM CPU
+ - 1 ARM Cortex-A8
+ - UART (SCI)
+ - 6
+ * - ARM MHz (Max.)
+ - 275,500,600,800,1000
+ - ADC
+ - 8-ch 12-bit
+ * - ARM MIPS (Max.)
+ - 1000,1200,2000
+ - PWM (Ch)
+ - 3
+ * - Graphics Acceleration
+ - 1 3D
+ - eCAP
+ - 3
+ * - Other Hardware Acceleration
+ - 2 PRU-ICSS,Crypto Accelerator
+ - eQEP
+ - 3
+ * - On-Chip L1 Cache
+ - 64 KB (ARM Cortex-A8)
+ - RTC
+ - 1
+ * - On-Chip L2 Cache
+ - 256 KB (ARM Cortex-A8)
+ - I2C
+ - 3
+ * - Other On-Chip Memory
+ - 128 KB
+ - McASP
+ - 2
+ * - Display Options
+ - LCD
+ - SPI
+ - 2
+ * - General Purpose Memory
+ - 1 16-bit (GPMC, NAND flash, NOR Flash, SRAM)
+ - DMA (Ch)
+ - 64-Ch EDMA
+ * - DRAM
+ - 1 16-bit (LPDDR-400,DDR2-532, DDR3-400)
+ - IO Supply (V)
+ - 1.8V(ADC),3.3V
+ * - USB Ports
+ - 2
+ - Operating Temperature Range (C)
+ - -40 to 90
+
+.. _documentation:
+
+Documentation
+***************
+
+Full documentation for the processor can be found on the TI website at `https://www.ti.com/product/TDA4VM <https://www.ti.com/product/TDA4VM>`_ for the current processor used on the board. Make sure that you always use the latest datasheets and Technical Reference Manuals (TRM).
+
+.. _crystal-circuitry:
+
+Crystal Circuitry
+******************
+
+:ref:`figure-30` is the crystal circuitry for the TDA4VM processor.
+
+.. _figure-30,Figure 30:
+
+.. figure:: media/image44.*
+ :width: 400px
+ :align: center
+
+ Processor Crystals
+
+.. _reset-circuitry:
+
+Reset Circuitry
+*****************
+
+:ref:`figure-31` is the board reset circuitry. The initial power on reset is generated by the
+**TPS65941213 and TPS65941111** power management IC. It also handles the reset for the Real Time Clock.
+
+The board reset is the SYS_RESETn signal. This is connected to the
+NRESET_INOUT pin of the processor. This pin can act as an input or an
+output. When the reset button is pressed, it sends a warm reset to the
+processor and to the system.
+
+On the revision A5D board, a change was made. On power up, the
+NRESET_INOUT signal can act as an output. In this instance it can cause
+the SYS_RESETn line to go high prematurely. In order to prevent this,
+the PORZn signal from the TPS65941213 and TPS65941111 is connected to the SYS_RESETn line
+using an open drain buffer. These ensure that the line does not
+momentarily go high on power up.
+
+.. _figure-31,Figure 31:
+
+.. figure:: media/image45.png
+ :width: 400px
+ :align: center
+
+ Board Reset Circuitry
+
+This change is also in all revisions after A5D.
+
+LPDDR4 Memory
+
+BeagleBone AI-64 uses a single MT41K256M16HA-125 512MB LPDDR4 device
+from Micron that interfaces to the processor over 16 data lines, 16
+address lines, and 14 control lines. On rev C we added the Kingston
+*KE4CN2H5A-A58* device as a source for the LPDDR4 device.
+
+The following sections provide more details on the design.
+
+.. _memory-device:
+
+Memory Device
+***************
+
+The design supports the standard DDR3 and LPDDR4 x16 devices and is built
+using the LPDDR4. A single x16 device is used on the board and there is
+no support for two x8 devices. The DDR3 devices work at 1.5V and the
+LPDDR4 devices can work down to 1.35V to achieve lower power. The LPDDR4 comes in a 96-BALL FBGA package
+with 0.8 mil pitch. Other standard DDR3 devices can also be supported,
+but the LPDDR4 is the lower power device and was chosen for its ability
+to work at 1.5V or 1.35V. The standard frequency that the LPDDR4 is run
+at on the board is 400MHZ.
+
+.. _ddr3l-memory-design:
+
+LPDDR4 Memory Design
+**********************
+
+:ref:`figure-32` is the schematic for the LPDDR4 memory device. Each of the
+groups of signals is described in the following lines.
+
+*Address Lines:* Provide the row address for ACTIVATE commands, and the
+column address and auto pre-charge bit (A10) for READ/WRITE commands, to
+select one location out of the memory array in the respective bank. A10
+sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address
+inputs also provide the op-code during a LOAD MODE command. Address
+inputs are referenced to VREFCA. A12/BC#: When enabled in the mode
+register (MR), A12 is sampled during READ and WRITE commands to
+determine whether burst chop (on-the-fly) will be performed (HIGH BL8
+or no burst chop, LOW BC4 burst chop).
+
+*Bank Address Lines:* BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA.
+
+*CK and CK# Lines:* are differential clock inputs. All address and
+control input signals are sampled on the crossing of the positive edge
+of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is
+referenced to the crossings of CK and CK#.
+
+*Clock Enable Line:* CKE enables (registered HIGH) and disables
+(registered LOW) internal circuitry and clocks on the DRAM. The specific
+circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM
+configuration and operating mode. Taking CKE LOW provides PRECHARGE
+power-down and SELF REFRESH operations (all banks idle) or active
+power-down (row active in any bank). CKE is synchronous for powerdown
+entry and exit and for self refresh entry. CKE is asynchronous for self
+refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT)
+are disabled during powerdown. Input buffers (excluding CKE and RESET#)
+are disabled during SELF REFRESH. CKE is referenced to VREFCA.
+
+.. _figure-32,Figure 32:
+
+.. figure:: media/image46.*
+ :width: 400px
+ :align: center
+
+ LPDDR4 Memory Design
+
+*Chip Select Line:* CS# enables (registered LOW) and disables
+(registered HIGH) the command decoder. All commands are masked when CS#
+is registered HIGH. CS# provides for external rank selection on systems
+with multiple ranks. CS# is considered part of the command code. CS# is
+referenced to VREFCA.
+
+*Input Data Mask Line:* DM is an input mask signal for write data. Input
+data is masked when DM is sampled HIGH along with the input data during
+a write access. Although the DM ball is input-only, the DM loading is
+designed to match that of the DQ and DQS balls. DM is referenced to
+VREFDQ.
+
+*On-die Termination Line:* ODT enables (registered HIGH) and disables
+(registered LOW) termination resistance internal to the LPDDR4 SDRAM.
+When enabled in normal operation, ODT is only applied to each of the
+following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS,
+DQS#, and DM for the x4. The ODT input is ignored if disabled via the
+LOAD MODE command. ODT is referenced to VREFCA.
+
+.. _power-rails-1:
+
+Power Rails
+******************
+
+The *LPDDR4* memory device and the DDR3 rails on the processor are
+supplied by the**TPS65941213 and TPS65941111**. Default voltage is 1.5V but can be scaled
+down to 1.35V if desired.
+
+.. _vref:
+
+VREF
+***************
+
+The *VREF* signal is generated from a voltage divider on the **VDDS_DDR**
+rail that powers the processor DDR rail and the LPDDR4 device itself.
+*Figure 33* below shows the configuration of this signal and the
+connection to the LPDDR4 memory device and the processor.
+
+.. _figure-33,Figure 33:
+
+.. figure:: media/image47.*
+ :width: 400px
+ :align: center
+
+ LPDDR4 VREF Design
+
+
+.. _gb-emmc-memory:
+
+4GB eMMC Memory
+-----------------
+
+The eMMC is a communication and mass data storage device that includes a
+Multi-MediaCard (MMC) interface, a NAND Flash component, and a
+controller on an advanced 11-signal bus, which is compliant with the MMC
+system specification. The nonvolatile eMMC draws no power to maintain
+stored data, delivers high performance across a wide range of operating
+temperatures, and resists shock and vibration disruption.
+
+One of the issues faced with SD cards is that across the different
+brands and even within the same brand, performance can vary. Cards use
+different controllers and different memories, all of which can have bad
+locations that the controller handles. But the controllers may be
+optimized for reads or writes. You never know what you will be getting.
+This can lead to varying rates of performance. The eMMC card is a known
+controller and when coupled with the 8bit mode, 8 bits of data instead
+of 4, you get double the performance which should result in quicker boot
+times.
+
+The following sections describe the design and device that is used on
+the board to implement this interface.
+
+.. _emmc-device:
+
+eMMC Device
+*************
+
+The device used is one of two different devices:
+
+* Micron *MTFC4GLDEA 0M WT*
+* Kingston *KE4CN2H5A-A58*
+
+The package is a 153 ball WFBGA device on both devices.
+
+.. _emmc-circuit-design:
+
+eMMC Circuit Design
+*********************
+
+:ref:`figure-34` is the design of the eMMC circuitry. The eMMC device is
+connected to the MMC1 port on the processor. MMC0 is still used for the
+microSD card as is currently done on the BeagleBone Black. The size
+of the eMMC supplied is now 4GB.
+
+The device runs at 3.3V both internally and the external I/O rails. The
+VCCI is an internal voltage rail to the device. The manufacturer
+recommends that a 1uF capacitor be attached to this rail, but a 2.2uF
+was chosen to provide a little margin.
+
+Pullup resistors are used to increase the rise time on the signals to
+compensate for any capacitance on the board.
+
+.. _figure-34,Figure 34:
+
+.. figure:: media/image48.*
+ :width: 400px
+ :align: center
+
+ eMMC Memory Design
+
+
+The pins used by the eMMC1 in the boot mode are listed below in *Table 6*.
+
+.. _table-6,Table 6:
+
+.. figure:: media/image49.*
+ :width: 400px
+ :align: center
+
+ eMMC Boot Pins
+
+For eMMC devices the ROM will only support raw mode. The ROM Code reads
+out raw sectors from image or the booting file within the file system
+and boots from it. In raw mode the booting image can be located at one
+of the four consecutive locations in the main area: offset 0x0 / 0x20000
+(128 KB) / 0x40000 (256 KB) / 0x60000 (384 KB). For this reason, a
+booting image shall not exceed 128KB in size. However it is possible to
+flash a device with an image greater than 128KB starting at one of the
+aforementioned locations. Therefore the ROM Code does not check the
+image size. The only drawback is that the image will cross the
+subsequent image boundary. The raw mode is detected by reading sectors
+#0, #256, #512, #768. The content of these sectors is then verified for
+presence of a TOC structure. In the case of a *GP Device*, a
+Configuration Header (CH)*must* be located in the first sector followed
+by a *GP header*. The CH might be void (only containing a CHSETTINGS
+item for which the Valid field is zero).
+
+The ROM only supports the 4-bit mode. After the initial boot, the switch
+can be made to 8-bit mode for increasing the overall performance of the
+eMMC interface.
+
+.. _board-id-eeprom:
+
+Board ID EEPROM
+-----------------
+
+BeagleBone is equipped with a single 32Kbit(4KB) 24LC32AT-I/OT
+EEPROM to allow the SW to identify the board. *Table 7* below defined
+the contents of the EEPROM.
+
+.. _table-7,Table 7:
+
+.. list-table:: Table 7: EEPROM Contents
+ :header-rows: 1
+
+ * - Name
+ - Size (bytes)
+ - Contents
+ * - Header
+ - 4
+ - 0xAA, 0x55, 0x33, EE
+ * - Board Name
+ - 8
+ - Name for board in ASCII: A335BNLT
+ * - Version
+ - 4
+ - Hardware version code for board in ASCII: 00A3 for Rev A3, 00A4 for Rev A4, 00A5 for Rev A5,00A6 for Rev A6,00B0 for Rev B, and 00C0 for Rev C.
+ * - Serial Number
+ - 12
+ - Serial number of the board. This is a 12 character string which is: WWYY4P16nnnn where: WW 2 digit week of the year of production YY 2 digit year of production BBBK BeagleBone AI-64 nnnn incrementing board number
+ * - Configuration Option
+ - 32
+ - Codes to show the configuration setup on this board.All FF
+ * - RSVD
+ - 6
+ - FF FF FF FF FF FF
+ * - RSVD
+ - 6
+ - FF FF FF FF FF FF
+ * - RSVD
+ - 6
+ - FF FF FF FF FF FF
+ * - Available
+ - 4018
+ - Available space for other non-volatile codes/data
+
+:ref:`figure-35` shows the new design on the EEPROM interface.
+
+.. _figure-35,Figure 35:
+
+.. figure:: media/image50.*
+ :width: 400px
+ :align: center
+
+ EEPROM Design Rev A5
+
+The EEPROM is accessed by the processor using the I2C 0 bus. The *WP*
+pin is enabled by default. By grounding the test point, the write
+protection is removed.
+
+The first 48 locations should not be written to if you choose to use the
+extras storage space in the EEPROM for other purposes. If you do, it
+could prevent the board from booting properly as the SW uses this
+information to determine how to set up the board.
+
+.. _micro-secure-digital:
+
+Micro Secure Digital
+----------------------
+
+The microSD connector on the board will support a microSD card that can
+be used for booting or file storage on BeagleBone AI-64.
+
+.. _microsd-design:
+
+microSD Design
+****************
+
+:ref:`figure-36` below is the design of the microSD interface on the board.
+
+.. _figure-36,Figure 36:
+
+.. figure:: media/image51.*
+ :width: 400px
+ :align: center
+
+ microSD Design
+
+The signals *MMC0-3* are the data lines for the transfer of data between
+the processor and the microSD connector.
+
+The *MMC0_CLK* signal clocks the data in and out of the microSD card.
+
+The *MMCO_CMD* signal indicates that a command versus data is being sent.
+
+There is no separate card detect pin in the microSD specification. It
+uses *MMCO_DAT3* for that function. However, most microSD connectors
+still supply a CD function on the connectors. In BeagleBone AI-64
+design, this pin is connected to the**MMC0_SDCD** pin for use by the
+processor. You can also change the pin to *GPIO0_6*, which is able to
+wake up the processor from a sleep mode when an microSD card is inserted
+into the connector.
+
+Pullup resistors are provided on the signals to increase the rise times
+of the signals to overcome PCB capacitance.
+
+Power is provided from the *VDD_3V3B* rail and a 10uF capacitor is
+provided for filtering.
+
+.. _user-leds:
+
+User LEDs
+-----------
+
+There are four user LEDs on BeagleBone AI-64. These are connected to
+GPIO pins on the processor. *Figure 37* shows the interfaces for the
+user LEDs.
+
+.. _figure-37,Figure 37:
+
+.. figure:: media/image52.*
+ :width: 400px
+ :align: center
+
+ User LEDs
+
+Resistors R71-R74 were changed to 4.75K on the revision A5B and later
+boards.
+
+:ref:`table-8` shows the signals used to control the four LEDs from the processor.
+
+.. _table-8,Table 8:
+
+.. list-table:: Table 8: User LED Control Signals/Pins
+ :header-rows: 1
+
+ * - LED
+ - GPIO SIGNAL
+ - PROC PIN
+ * - USR0
+ - GPIO1_21
+ - V15
+ * - USR1
+ - GPIO1_22
+ - U15
+ * - USR2
+ - GPIO1_23
+ - T15
+ * - USR3
+ - GPIO1_24
+ - V16
+
+
+
+A logic level of “1†will cause the LEDs to turn on.
+
+.. _boot-configuration:
+
+Boot Configuration
+--------------------
+
+The design supports two groups of boot options on the board. The user
+can switch between these modes via the Boot button. The primary boot
+source is the onboard eMMC device. By holding the Boot button, the user
+can force the board to boot from the microSD slot. This enables the eMMC
+to be overwritten when needed or to just boot an alternate image. The
+following sections describe how the boot configuration works.
+
+In most applications, including those that use the provided demo
+distributions available from `beagleboard.org <http://beagleboard.org/>`_
+the processor-external boot code is composed of two stages. After the
+primary boot code in the processor ROM passes control, a secondary stage
+(secondary program loader -- "SPL" or "MLO") takes over. The SPL stage
+initializes only the required devices to continue the boot process, and
+then control is transferred to the third stage "U-boot". Based on the
+settings of the boot pins, the ROM knows where to go and get the SPL and
+UBoot code. In the case of BeagleBone AI-64, that is either eMMC or
+microSD based on the position of the boot switch.
+
+.. _boot-configuration-design:
+
+Boot Configuration Design
+****************************
+
+:ref:`figure-38` shows the circuitry that is involved in the boot
+configuration process. On power up, these pins are read by the processor
+to determine the boot order. S2 is used to change the level of one bit
+from HI to LO which changes the boot order.
+
+.. _figure-38,Figure 38:
+
+.. figure:: media/image53.*
+ :width: 400px
+ :align: center
+
+ Processor Boot Configuration Design
+
+It is possible to override these setting via the expansion headers. But
+be careful not to add too much load such that it could interfere with
+the operation of the display interface or LCD panels. If you choose to
+override these settings, it is strongly recommended that you gate these
+signals with the *SYS_RESETn* signal. This ensures that after coming out
+of reset these signals are removed from the expansion pins.
+
+.. _default-boot-options:
+
+Default Boot Options
+----------------------
+
+Based on the selected option found in :ref:`figure-39` below, each of the
+boot sequences for each of the two settings is shown.
+
+.. _figure-39,Figure 39:
+
+.. figure:: media/image54.*
+ :width: 400px
+ :align: center
+
+ Processor Boot Configuration
+
+The first row in :ref:`figure-39` is the default setting. On boot, the
+processor will look for the eMMC on the MMC1 port first, followed by the
+microSD slot on MMC0, USB0 and UART0. In the event there is no microSD
+card and the eMMC is empty, UART0 or USB0 could be used as the board
+source.
+
+If you have a microSD card from which you need to boot from, hold the
+boot button down. On boot, the processor will look for the SPIO0 port
+first, then microSD on the MMC0 port, followed by USB0 and UART0. In the
+event there is no microSD card and the eMMC is empty, USB0 or UART0
+could be used as the board source.
+
+.. _ethernet:
+
+10/100/1000 Ethernet
+----------------------
+
+BeagleBone AI-64 is equipped with a 10/100/1000 Ethernet interface.
+The design is
+described in the following sections.
+
+.. _ethernet-processor-interface:
+
+Ethernet Processor Interface
+*******************************
+
+:ref:`figure-40` shows the connections between the processor and the PHY. The
+interface is in the MII mode of operation.
+
+.. _figure-40,Figure 40:
+
+.. figure:: media/image55.*
+ :width: 400px
+ :align: center
+
+ Ethernet Processor Interface
+
+
+This is the same interface as is used on BeagleBone. No changes were
+made in this design for the board.
+
+.. _ethernet-connector-interface:
+
+Ethernet Connector Interface
+*********************************************
+
+The off board side of the PHY connections are shown in *Figure 41*
+below.
+
+.. _figure-41,Figure 41:
+
+.. figure:: media/image56.*
+ :width: 400px
+ :align: center
+
+ Ethernet Connector Interface
+
+This is the same interface as is used on BeagleBone. No changes were
+made in this design for the board.
+
+.. _ethernet-phy-power-reset-and-clocks:
+
+Ethernet PHY Power, Reset, and Clocks
+*********************************************
+
+:ref:`figure-42` shows the power, reset, and lock connections to
+the **LAN8710A** PHY. Each of these areas is discussed in more detail in
+the following sections.
+
+.. _figure-42,Figure 42:
+
+.. figure:: media/image57.*
+ :width: 400px
+ :align: center
+
+ Ethernet PHY, Power, Reset, and Clocks
+
+
+VDD_3V3B Rail
+*****************
+
+The VDD_3V3B rail is the main power rail for the *LAN8710A*. It
+originates at the VD_3V3B regulator and is the primary rail that
+supports all of the peripherals on the board. This rail also supplies
+the VDDIO rails which set the voltage levels for all of the I/O signals
+between the processor and the **LAN8710A**.
+
+VDD_PHYA Rail
+*******************
+
+A filtered version of VDD_3V3B rail is connected to the VDD rails of the
+LAN8710 and the termination resistors on the Ethernet signals. It is
+labeled as *VDD_PHYA*. The filtering inductor helps block transients
+that may be seen on the VDD_3V3B rail.
+
+PHY_VDDCR Rail
+*********************
+
+The *PHY_VDDCR* rail originates inside the LAN8710A. Filter and bypass
+capacitors are used to filter the rail. Only circuitry inside the
+LAN8710A uses this rail.
+
+SYS_RESET
+******************
+
+The reset of the LAN8710A is controlled via the *SYS_RESETn* signal, the
+main board reset line.
+
+Clock Signals
+*********************
+
+A crystal is used to create the clock for the LAN8710A. The processor
+uses the *RMII_RXCLK* signal to provide the clocking for the data
+between the processor and the LAN8710A.
+
+.. _lan8710a-mode-pins:
+
+LAN8710A Mode Pins
+*********************
+
+There are mode pins on the LAN8710A that sets the operational mode for
+the PHY when coming out of reset. These signals are also used to
+communicate between the processor and the LAN8710A. As a result, these
+signals can be driven by the processor which can cause the PHY not to be
+initialized correctly. To ensure that this does not happen, three low
+value pull up resistors are used. *Figure 43* below shows the three mode
+pin resistors.
+
+.. _figure-43,Figure 43:
+
+.. figure:: media/image97.*
+ :width: 400px
+ :align: center
+
+ Ethernet PHY Mode Pins
+
+This will set the mode to be 111, which enables all modes and enables
+auto-negotiation.
+
+.. _hdmi-interface-1:
+
+Display Port Interface
+-----------------------------------
+
+BeagleBone AI-64 has an onboard Display Port framer that converts the LCD
+signals and audio signals to drive a Display Port monitor. The design uses the on chip
+internal Display Port Framer.
+
+The following sections provide more detail into the design of this
+interface.
+
+.. _supported-resolutions:
+
+Supported Resolutions
+****************************
+
+The maximum resolution supported by BeagleBone AI-64 is 1280x1024 @
+60Hz. *Table 9* below shows the supported resolutions. Not all
+resolutions may work on all monitors, but these have been tested and
+shown to work on at least one monitor. EDID is supported on the
+BeagleBone AI-64. Based on the EDID reading from the connected monitor,
+the highest compatible resolution is selected.
+
+.Table 9. HDMI Supported Monitor Adapter Resolutions
+[cols"4,1",options"header",]
+
+.. list-table:: Table 9. HDMI Supported Monitor Adapter Resolutions
+ :header-rows: 1
+
+ * - RESOLUTION
+ - AUDIO
+ * - 800 x 600 @60Hz
+ -
+ * - 800 x 600 @56Hz
+ -
+ * - 640 x 480 @75Hz
+ -
+ * - 640 x 480 @60Hz
+ - YES
+ * - 720 x 400 @70Hz
+ -
+ * - 1280 x 1024 @75Hz
+ -
+ * - 1024 x 768 @75Hz
+ -
+ * - 1024 x 768 @70Hz
+ -
+ * - 1024 x 768 @60Hz
+ -
+ * - 800 x 600 @75Hz
+ -
+ * - 800 x 600 @72Hz
+ -
+ * - 720 x 480 @60Hz
+ - YES
+ * - 1280 x 720 @60Hz
+ - YES
+ * - 1920x1080 @24Hz
+ - YES
+
+
+.. note ::
+
+ The updated software image used on the Rev A5B and later boards added support for 1920x1080@24HZ.
+
+
+Audio is limited to CEA supported resolutions. LCD panels only activate
+the audio in CEA modes. This is a function of the specification and is
+not something that can be fixed on the board via a hardware change or a
+software change.
+
+.. _hdmi-framer:
+
+Display Port Framer
+*********************************************
+
+insert processor Display Port framer doc here
+
+.. _hdmi-video-processor-interface:
+
+Display Port Video Processor Interface
+*********************************************
+
+insert processor Display Port V-interface doc here
+
+.. _hdmi-control-processor-interface:
+
+Display Port Control Processor Interface
+*********************************************
+
+insert processor Display Port C-interface doc here
+
+.. _interrupt-signal:
+
+Interrupt Signal
+*********************************************
+
+insert processor Display Port interrupt doc here
+
+.. _audio-interface:
+
+Audio Interface
+*********************************************
+
+insert processor Display Port audio doc here
+
+.. _power-connections:
+
+Power Connections
+*********************************************
+
+guesing this doesn’t exist on this device
+
+.. _hdmi-connector-interface:
+
+miniDP Connector Interface
+*********************************************
+
+insert processor Mini Display Port connector doc here
+
+.. _usb-host:
+
+USB Host
+-----------------------------------
+
+The board is equipped with a single USB host interface accessible from a
+single USB Type A female connector. :ref:`figure-48` is the design of the USB
+Host circuitry.
+
+.. _figure-48,Figure 48:
+
+.. figure:: media/image66.*
+ :width: 400px
+ :align: center
+
+ USB Host circuit
+
+.. _power-switch:
+
+Power Switch
+*********************************************
+
+*U8* is a switch that allows the power to the connector to be turned on
+or off by the processor. It also has an over current detection that can
+alert the processor if the current gets too high via the**USB1_OC**
+signal. The power is controlled by the *USB1_DRVBUS* signal from the
+processor.
+
+.. _esd-protection:
+
+ESD Protection
+*********************************************
+
+*U9* is the ESD protection for the signals that go to the connector.
+
+.. _filter-options:
+
+Filter Options
+*********************************************
+
+*FB7* and *FB8* were added to assist in passing the FCC emissions test.
+The *USB1_VBUS* signal is used by the processor to detect that the 5V is
+present on the connector. *FB7* is populated and *FB8* is replaced with
+a .1 ohm resistor.
+
+.. _pru-icss:
+
+PRU-ICSS
+-----------------------------------
+
+The PRU-ICSS module is located inside the TDA4VM processor. Access to
+these pins is provided by the expansion headers and is multiplexed with
+other functions on the board. Access is not provided to all of the
+available pins.
+
+All documentation is located at http://git.beagleboard.org/beagleboard/am335x_pru_package
+
+This feature is not supported by Texas Instruments.
+
+.. _pru-icss-features:
+
+PRU-ICSS Features
+*********************************************
+
+The features of the PRU-ICSS include:
+
+Two independent programmable real-time (PRU) cores:
+
+* 32-Bit Load/Store RISC architecture
+* 8K Byte instruction RAM (2K instructions) per core
+* 8K Bytes data RAM per core
+* 12K Bytes shared RAM
+* Operating frequency of 200 MHz
+* PRU operation is little endian similar to ARM processor
+* All memories within PRU-ICSS support parity
+* Includes Interrupt Controller for system event handling
+* Fast I/O interface
+
+*16 input pins and 16 output pins per PRU core. (Not all of these are
+accessible on BeagleBone AI-64).*
+
+.. _pru-icss-block-diagram:
+
+PRU-ICSS Block Diagram
+*****************************
+
+:ref:`figure-49` is a high level block diagram of the PRU-ICSS.
+
+.. _figure-49,Figure 49:
+
+.. figure:: media/image67.*
+ :width: 400px
+ :align: center
+
+ PRU-ICSS Block Diagram
+
+.. _pru-icss-pin-access:
+
+PRU-ICSS Pin Access
+*********************************************
+
+Both PRU 0 and PRU1 are accessible from the expansion headers. Some may
+not be useable without first disabling functions on the board like LCD
+for example. Listed below is what ports can be accessed on each PRU.
+
+* 8 outputs or 9 inputs PRU1
+* 13 outputs or 14 inputs
+* UART0_TXD, UART0_RXD, UART0_CTS, UART0_RTS
+
+:ref:`table-11` below shows which PRU-ICSS signals can be accessed on the
+BeagleBone AI-64 and on which connector and pins they are accessible
+from. Some signals are accessible on the same pins.
+
+.. _table-11,Table 11:
+
+.. list-table:: PRU0 and PRU1 Access
+ :header-rows: 1
+
+ * -
+ - PIN
+ - PROC
+ - NAME
+ -
+ -
+ -
+ * - P8
+ - 11
+ - R12
+ - GPIO1_13
+ -
+ - pr1_pru0_pru_r30_15 (Output)
+ -
+ * -
+ - 12
+ - T12
+ - GPIO1_12
+ -
+ - pr1_pru0_pru_r30_14 (Output)
+ -
+ * -
+ - 15
+ - U13
+ - GPIO1_15
+ -
+ - pr1_pru0_pru_r31_15 (Input)
+ -
+ * -
+ - 16
+ - V13
+ - GPIO1_14
+ -
+ - pr1_pru0_pru_r31_14 (Input)
+ -
+ * -
+ - 20
+ - V9
+ - GPIO1_31
+ - pr1_pru1_pru_r30_13 (Output)
+ - pr1_pru1_pru_r31_13 (INPUT)
+ -
+ * -
+ - 21
+ - U9
+ - GPIO1_30
+ - pr1_pru1_pru_r30_12 (Output)
+ - pr1_pru1_pru_r31_12 (INPUT)
+ -
+ * -
+ - 27
+ - U5
+ - GPIO2_22
+ - pr1_pru1_pru_r30_8 (Output)
+ - pr1_pru1_pru_r31_8 (INPUT)
+ -
+ * -
+ - 28
+ - V5
+ - GPIO2_24
+ - pr1_pru1_pru_r30_10 (Output)
+ - pr1_pru1_pru_r31_10 (INPUT)
+ -
+ * -
+ - 29
+ - R5
+ - GPIO2_23
+ - pr1_pru1_pru_r30_9 (Output)
+ - pr1_pru1_pru_r31_9 (INPUT)
+ -
+ * -
+ - 39
+ - T3
+ - GPIO2_12
+ - pr1_pru1_pru_r30_6 (Output)
+ - pr1_pru1_pru_r31_6 (INPUT)
+ -
+ * -
+ - 40
+ - T4
+ - GPIO2_13
+ - pr1_pru1_pru_r30_7 (Output)
+ - pr1_pru1_pru_r31_7 (INPUT)
+ -
+ * -
+ - 41
+ - T1
+ - GPIO2_10
+ - pr1_pru1_pru_r30_4 (Output)
+ - pr1_pru1_pru_r31_4 (INPUT)
+ -
+ * -
+ - 42
+ - T2
+ - GPIO2_11
+ - pr1_pru1_pru_r30_5 (Output)
+ - pr1_pru1_pru_r31_5 (INPUT)
+ -
+ * -
+ - 43
+ - R3
+ - GPIO2_8
+ - pr1_pru1_pru_r30_2 (Output)
+ - pr1_pru1_pru_r31_2 (INPUT)
+ -
+ * -
+ - 44
+ - R4
+ - GPIO2_9
+ - pr1_pru1_pru_r30_3 (Output)
+ - pr1_pru1_pru_r31_3 (INPUT)
+ -
+ * -
+ - 45
+ - R1
+ - GPIO2_6
+ - pr1_pru1_pru_r30_0 (Output)
+ - pr1_pru1_pru_r31_0 (INPUT)
+ -
+ * -
+ - 46
+ - R2
+ - GPIO2_7
+ - pr1_pru1_pru_r30_1 (Output)
+ - pr1_pru1_pru_r31_1 (INPUT)
+ -
+ * -
+ -
+ -
+ -
+ -
+ -
+ -
+ * - P9
+ - 17
+ - A16
+ - I2C1_SCL
+ - pr1_uart0_txd
+ -
+ -
+ * -
+ - 18
+ - B16
+ - I2C1_SDA
+ - pr1_uart0_rxd
+ -
+ -
+ * -
+ - 19
+ - D17
+ - I2C2_SCL
+ - pr1_uart0_rts_n
+ -
+ -
+ * -
+ - 20
+ - D18
+ - I2C2_SDA
+ - pr1_uart0_cts_n
+ -
+ -
+ * -
+ - 21
+ - B17
+ - UART2_TXD
+ - pr1_uart0_rts_n
+ -
+ -
+ * -
+ - 22
+ - A17
+ - UART2_RXD
+ - pr1_uart0_cts_n
+ -
+ -
+ * -
+ - 24
+ - D15
+ - UART1_TXD
+ - pr1_uart0_txd
+ - pr1_pru0_pru_r31_16 (Input)
+ -
+ * -
+ - 25
+ - A14
+ - GPIO3_21footnote:[GPIO3_21 is also the 24.576MHZ clock input to the processor to enable HDMI audio. To use this pin the oscillator must be disabled.]
+ - pr1_pru0_pru_r30_5 (Output)
+ - pr1_pru0_pru_r31_5 (Input)
+ -
+ * -
+ - 26
+ - D16
+ - UART1_RXD
+ - pr1_uart0_rxd
+ - pr1_pru1_pru_r31_16
+ -
+ * -
+ - 27
+ - C13
+ - GPIO3_19
+ - pr1_pru0_pru_r30_7 (Output)
+ - pr1_pru0_pru_r31_7 (Input)
+ -
+ * -
+ - 28
+ - C12
+ - SPI1_CS0
+ - eCAP2_in_PWM2_out
+ - pr1_pru0_pru_r30_3 (Output)
+ - pr1_pru0_pru_r31_3 (Input)
+ * -
+ - 29
+ - B13
+ - SPI1_D0
+ - pr1_pru0_pru_r30_1 (Output)
+ - pr1_pru0_pru_r31_1 (Input)
+ -
+ * -
+ - 30
+ - D12
+ - SPI1_D1
+ - pr1_pru0_pru_r30_2 (Output)
+ - pr1_pru0_pru_r31_2 (Input)
+ -
+ * -
+ - 31
+ - A13
+ - SPI1_SCLK
+ - pr1_pru0_pru_r30_0 (Output)
+ - pr1_pru0_pru_r31_0 (Input)
+ -
+
+:orphan:
+
+.. _bbai64-cape-board-support-1:
+
+Cape Board Support
+#######################
+
+*BeagleBone AI-64* has the ability to accept up to
+four EEPROM addressable expansion boards or capes stacked onto
+the expansion headers. The word cape comes from the shape of the
+expansion board for BeagleBone boards as it is fitted around the
+Ethernet connector on the main board. For BeagleBone this notch acts as a
+key to ensure proper orientation of the cape. On AI-64 you can see a clear
+silkscreen marking for the cape orientation. Most of BeagleBone capes
+can be used with your BeagleBone AI-64 also like shown in :ref:`bbai64-cape-placement-figure` below.
+
+.. _bbai64-cape-placement-figure:
+
+.. figure:: media/ch08/cape-placement.*
+ :width: 400px
+ :align: center
+
+ BeagleBone AI-64 cape placement
+
+This section describes the rules & guidelines for creating capes to ensure proper
+operation with BeagleBone AI-64 and proper interoperability with
+other capes that are intended to coexist with each other. Co-existence
+is not a requirement and is in itself, something that is impossible to
+control or administer. But, people will be able to create capes that
+operate with other capes that are already available based on public
+information as it pertains to what pins and features each cape uses.
+This information will be able to be read from the EEPROM on each cape.
+
+For those wanting to create their own capes this should not put limits on the creation of
+capes and what they can do, but may set a few basic rules that will allow
+the software to administer their operation with BeagleBone AI-64. For this
+reason there is a lot of flexibility in the specification that we hope
+most people will find it liberating in the spirit of Open Source
+Hardware. On the other hand we are sure that there are others who would like to see tighter
+control, more details, more rules and much more order to the way capes
+are handled.
+
+Over time, this specification will change and be updated, so please
+refer to the `latest version of this manual <https://git.beagleboard.org/beagleboard/beaglebone-ai-64/>`_
+prior to designing your own capes to get the latest information.
+
+.. warning::
+
+ Do not apply voltage to any I/O pin when power is not supplied to the board.
+ It will damage the processor and void the warranty.
+
+.. _beaglebone-ai-64-cape-compatibility:
+
+BeagleBone AI-64 Cape Compatibility
+-------------------------------------------
+
+The expansion headers on BeagleBone Black and BeagleBone AI-64 provides
+similar pin configuration options on P8 and P9 expansion header pins thus provide
+cape compatibility to a certain extent. Which means most BeagleBone Black capes
+will also be compatible with BeeagleBone AI-64.
+
+.. important::
+
+ This section is still being worked on, please make sure you have the latest system reference manual (SRM).
+
+
+.. todo
+
+ Add BeagleBone AI-64 LCD pins information.
+ Add BeagleBone AI-64 eMMC pins information.
+
+
+.. _eeprom:
+
+EEPROM
+-------------------------------------------
+
+Each cape must have its own EEPROM containing information that will
+allow the software to identify the board and to configure the expansion
+headers pins during boot as needed. The one exception is proto boards intended for
+prototyping. They may or may not have an EEPROM on them. An EEPROM is
+required for all capes sold in order for them operate correctly when
+plugged into BeagleBone AI-64.
+
+The address of the EEPROM will be set via either jumpers or a dipswitch
+on each expansion board. :ref:`expansion-board-eeprom-without-write-protect-figure`
+below is the design of the EEPROM circuit.
+
+.. _expansion-board-eeprom-without-write-protect-figure:
+
+.. figure:: media/ch08/eeprom.*
+ :width: 400px
+ :align: center
+
+ Expansion board EEPROM without write protect
+
+The addressing of this device requires two bytes for the address which
+is not used on smaller size EEPROMs, which only require only one byte.
+Other compatible devices may be used as well. Make sure the device you
+select supports 16 bit addressing. The part package used is at the
+discretion of the cape designer.
+
+.. _eeprom-address:
+
+EEPROM Address
+***************************
+
+In order for each cape to have a unique address, a board ID scheme is
+used that sets the address to be different depending on the setting of
+the dipswitch or jumpers on the capes. A two position dipswitch or
+jumpers is used to set the address pins of the EEPROM.
+
+It is the responsibility of the user to set the proper address for each
+board and the position in the stack that the board occupies has nothing
+to do with which board gets first choice on the usage of the expansion
+bus signals. The process for making that determination and resolving
+conflicts is left up to the SW and, as of this moment in time, this
+method is a something of a mystery due to the new Device Tree
+methodology introduced in the 3.8 kernel.
+
+Address line A2 is always tied high. This sets the allowable address
+range for the expansion cards to *0x54* to**0x57**. All other I2C
+addresses can be used by the user in the design of their capes. But,
+these addresses must not be used other than for the board EEPROM
+information. This also allows for the inclusion of EEPROM devices on the
+cape if needed without interfering with this EEPROM. It requires that A2
+be grounded on the EEPROM not used for cape identification.
+
+.. _i2c-bus:
+
+I2C Bus
+***************************
+
+The EEPROMs on each expansion board are connected to I2C2 on connector
+P9 pins 19 and 20. For this reason I2C2 must always be left connected
+and should not be changed by SW to remove it from the expansion header
+pin mux settings. If this is done, the system will be unable to detect
+the capes.
+
+The I2C signals require pullup resistors. Each board must have a 5.6K
+resistor on these signals. With four capes installed this will result in
+an effective resistance of 1.4K if all capes were installed and all the
+resistors used were exactly 5.6K. As more capes are added the resistance
+is reduced to overcome capacitance added to the signals. When no capes
+are installed the internal pullup resistors must be activated inside the
+processor to prevent I2C timeouts on the I2C bus.
+
+The I2C2 bus may also be used by capes for other functions such as I/O
+expansion or other I2C compatible devices that do not share the same
+address as the cape EEPROM.
+
+.. _eeprom-write-protect:
+
+EEPROM Write Protect
+***************************
+
+The design in :ref:`expansion-board-eeprom-with-write-protect-figure`
+has the write protect disabled. If the write
+protect is not enabled, this does expose the EEPROM to being corrupted
+if the I2C2 bus is used on the cape and the wrong address written to. It
+is recommended that a write protection function be implemented and a
+Test Point be added that when grounded, will allow the EEPROM to be
+written to. To enable write operation, Pin 7 of the EEPROM must be tied
+to ground.
+
+When not grounded, the pin is HI via pullup resistor R210 and therefore
+write protected. Whether or not Write Protect is provided is at the
+discretion of the cape designer.
+
+*Variable & MAC Memory*
+
+VSYS_IO_3V3
+
+.. _expansion-board-eeprom-with-write-protect-figure:
+
+.. figure:: media/ch08/eeprom-write-protect.*
+ :width: 400px
+ :align: center
+
+ Expansion board EEPROM with write protect
+
+.. _eeprom-data-format:
+
+EEPROM Data Format
+===================
+
+:ref:`expansion-board-eeprom-table`
+shows the format of the contents of the expansion board
+EEPROM. Data is stored in Big Endian with the least significant value on
+the right. All addresses read as a single byte data from the EEPROM, but
+two byte addressing is used. ASCII values are intended to be easily read
+by the user when the EEPROM contents are dumped.
+
+*Clean/Update table*
+
+.. _expansion-board-eeprom-table:
+
+.. list-table:: Expansion Board EEPROM
+ :header-rows: 1
+
+ * - Name
+ - Offset
+ - Size (bytes)
+ - Contents
+ * - Header
+ - 0
+ - 4
+ - 0xAA, 0x55, 0x33, 0xEE
+ * - EEPROM Revision
+ - 4
+ - 2
+ - Revision number of the overall format of this EEPROM in ASCII =A1
+ * - Board Name
+ - 6
+ - 32
+ - Name of board in ASCII so user can read it when the EEPROM is dumped. Up to developer of the board as to what they call the board..
+ * - Version
+ - 38
+ - 4
+ - Hardware version code for board in ASCII.Version format is up to the developer.i.e. 02.1…00A1....10A0
+ * - Manufacturer
+ - 42
+ - 16
+ - ASCII name of the manufacturer. Company or individual’s name.
+ * - Part Number
+ - 58
+ - 16
+ - ASCII Characters for the part number. Up to maker of the board.
+ * - Number of Pins
+ - 74
+ - 2
+ - Number of pins used by the daughter board including the power pins used. Decimal value of total pins 92 max, stored in HEX.
+ * - Serial Number
+ - 76
+ - 12
+ - Serial number of the board. This is a 12 character string which is: **WWYY&&&&nnnn** where, WW = 2 digit week of the year of production, YY = 2 digit year of production , &&&&=Assembly code to let the manufacturer document the assembly number or product. A way to quickly tell from reading the serial number what the board is. Up to the developer to determine. nnnn = incrementing board number for that week of production
+ * - Pin Usage
+ - 88
+ - 148
+ - Two bytes for each configurable pins of the 74 pins on the expansion connectors, MSB LSB Bit order: 15..14 ..... 1..0 Bit 15....Pin is used or not...0=Unused by cape 1=Used by cape Bit 14-13...Pin Direction.....1 0=Output 01=Input 11=BDIR Bits 12-7...Reserved........should be all zeros Bit 6....Slew Rate .......0=Fast 1=Slow Bit 5....Rx Enable.......0=Disabled 1=Enabled Bit 4....Pull Up/Dn Select....0=Pulldown 1=PullUp Bit 3....Pull Up/DN enabled...0=Enabled 1=Disabled Bits 2-0 ...Mux Mode Selection...Mode 0-7
+ * - VDD_3V3B Current
+ - 236
+ - 2
+ - Maximum current in milliamps. This is HEX value of the current in decimal 1500mA=0x05 0xDC 325mA=0x01 0x45
+ * - VDD_5V Current
+ - 238
+ - 2
+ - Maximum current in milliamps. This is HEX value of the current in decimal 1500mA=0x05 0xDC 325mA=0x01 0x45
+ * - SYS_5V Current
+ - 240
+ - 2
+ - Maximum current in milliamps. This is HEX value of the current in decimal 1500mA=0x05 0xDC 325mA=0x01 0x45
+ * - DC Supplied
+ - 242
+ - 2
+ - Indicates whether or not the board is supplying voltage on the VDD_5V rail and the current rating 000=No 1-0xFFFF is the current supplied storing the decimal quivalent in HEX format
+ * - Available
+ - 244
+ - 32543
+ - Available space for other non-volatile codes/data to be used as needed by the manufacturer or SW driver. Could also store presets for use by SW.
+
+.. _pin-usage:
+
+Pin Usage
+==========
+
+:ref:`eeprom-pin-usage-table` shows the locations in the EEPROM to set the I/O pin usage for
+the cape. It contains the value to be written to the Pad Control
+Registers. Details on this can be found in section *9.2.2* of the
+*TDA4VM Technical Reference Manual*, The table is left blank as a
+convenience and can be printed out and used as a template for creating a
+custom setting for each cape. The 16 bit integers and all 16 bit fields
+are to be stored in Big Endian format.
+
+**Bit 15 PIN USAGE** is an indicator and should be a 1 if the pin is used or 0 if it is unused.
+
+**Bits 14-7 RESERVED** is not to be used and left as 0.
+
+**Bit 6 SLEW CONTROL** 0=Fast 1=Slow
+
+**Bit 5 RX Enabled** 0=Disabled 1=Enabled
+
+**Bit 4 PU/PD** 0=Pulldown 1=Pullup.
+
+**Bit 3 PULLUP/DN** 0=Pullup/pulldown enabled 1= Pullup/pulldown disabled
+
+**Bit 2-0 MUX MODE SELECT** Mode 0-7. (refer to TRM)
+
+Refer to the TRM for proper settings of the pin MUX mode based on the
+signal selection to be used.
+
+The *AIN0-6* pins do not have a pin mux setting, but they need to be set
+to indicate if each of the pins is used on the cape. Only bit 15 is used
+for the AIN signals.
+
+
+
+.. _eeprom-pin-usage-table:
+
+.. list-table:: EEPROM Pin Usage
+ :header-rows: 1
+
+
+ * - `+`
+ - `+`
+ - `+`
+ - **15**
+ - **14**
+ - **13**
+ - **12**
+ - **11**
+ - **10**
+ - **9**
+ - **8**
+ - **7**
+ - **6**
+ - **5**
+ * - **Off set**
+ - **Conn**
+ - **Name**
+ - **Pin Usage**
+ - **Type**
+ - `+`
+ - **Reserved**
+ - `+`
+ - `+`
+ - **S L E W**
+ - **R X**
+ - **P U - P D**
+ - **P U / D E N**
+ - **Mux Mode**
+ * - **88**
+ - **P9-22**
+ - **UART2_RXD**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **90**
+ - **P9-21**
+ - **UART2_TXD**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **92**
+ - **P9-18**
+ - **I2C1_SDA**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **94**
+ - **P9-17**
+ - **I2C1_SCL**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **96**
+ - **P9-42**
+ - **GPIO0_7**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **98**
+ - **P8-35**
+ - **UART4_CTSN**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **100**
+ - **P8-33**
+ - **UART4_RTSN**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **102**
+ - **P8-31**
+ - **UART5_CTSN**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **104**
+ - **P8-32**
+ - **UART5_RTSN**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **106**
+ - **P9-19**
+ - **I2C2_SCL**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **108**
+ - **P9-20**
+ - **I2C2_SDA**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **110**
+ - **P9-26**
+ - **UAR*T1_RXD**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **112**
+ - **P9-24**
+ - **UART1_TXD**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **114**
+ - **P9-41**
+ - **CLKOUT2**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **116**
+ - **P8-19**
+ - **EHRPWM2A**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **118**
+ - **P8-13**
+ - **EHRPWM2B**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **120**
+ - **P8-14**
+ - **GPIO0_26**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **122**
+ - **P8-17**
+ - **GPIO0_27**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **124**
+ - **P9-11**
+ - **UART4_RXD**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **126**
+ - **P9-13**
+ - **UART4_TXD**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **128**
+ - **P8-25**
+ - **GPIO1_0**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **130**
+ - **P8-24**
+ - **GPIO1_1**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **132**
+ - **P8-5**
+ - **GPIO1_2**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **134**
+ - **P8-6**
+ - **GPIO1_3**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **136**
+ - **P8-23**
+ - **GPIO1_4**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **138**
+ - **P8-22**
+ - **GPIO1_5**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **140**
+ - **P8-3**
+ - **GPIO1_6**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **142**
+ - **P8-4**
+ - **GPIO1_7**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **144**
+ - **P8-12**
+ - **GPIO1_12**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **146**
+ - **P8-11**
+ - **GPIO1_13**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **148**
+ - **P8-16**
+ - **GPIO1_14**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **150**
+ - **P8-15**
+ - **GPIO1_15**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - **152**
+ - **P9-15**
+ - **GPIO1_16**
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+
+
+.. list-table::
+ :header-rows: 1
+
+ * -
+ -
+ -
+ - 15
+ - 14
+ - 13
+ - 12
+ - 11
+ - 10
+ - 9
+ - 8
+ - 7
+ - 6
+ - 5
+ * - Off set
+ - Conn
+ - Name
+ - Pin Usage
+ - Type
+ - `+`
+ - Reserve
+ - `+`
+ - `+`
+ - S L E W
+ - R X
+ - P U - P D
+ - P U / DE N
+ - Mux Mode
+ * - 154
+ - P9-23
+ - GPIO1_17
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ * - 156
+ - P9-14
+ - EHRPWM1A
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ * - 158
+ - P9-16
+ - EHRPWM1B
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ * - 160
+ - P9-12
+ - GPIO1_28
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ * - 162
+ - P8-26
+ - GPIO1_29
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ * - 164
+ - P8-21
+ - GPIO1_30
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ * - 166
+ - P8-20
+ - GPIO1_31
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ * - 168
+ - P8-18
+ - GPIO2_1
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ * - 170
+ - P8-7
+ - TIMER4
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ * - 172
+ - P8-9
+ - TIMER5
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 174
+ - P8-10
+ - TIMER6
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 176
+ - P8-8
+ - TIMER7
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 178
+ - P8-45
+ - GPIO2_6
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 180
+ - P8-46
+ - GPIO2_7
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 182
+ - P8-43
+ - GPIO2_8
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 184
+ - P8-44
+ - GPIO2_9
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 186
+ - P8-41
+ - GPIO2_10
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 188
+ - P8-42
+ - GPIO2_11
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 190
+ - P8-39
+ - GPIO2_12
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 192
+ - P8-40
+ - GPIO2_13
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 194
+ - P8-37
+ - UART5_TX`+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 196
+ - P8-38
+ - UART5_RX`+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 198
+ - P8-36
+ - UART3_CTSN
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 200
+ - P8-34
+ - UART3_RTSN
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 202
+ - P8-27
+ - GPIO2_22
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 204
+ - P8-29
+ - GPIO2_23
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 206
+ - P8-28
+ - GPIO2_24
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 208
+ - P8-30
+ - GPIO2_25
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 210
+ - P9-29
+ - SPI1_D0
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 212
+ - P9-30
+ - SPI1_D1
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 214
+ - P9-28
+ - SPI1_CS0
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 216
+ - P9-27
+ - GPIO3_19
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 218
+ - P9-31
+ - SPI1_SCLK
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 220
+ - P9-25
+ - GPIO3_21
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - `+`
+ - `+`
+ - `+`
+ - 15
+ - 14
+ - 13
+ - 12
+ - 11
+ - 10
+ - 9
+ - 8
+ - 7
+ - 6
+ - 5
+ * - Off set
+ - Conn
+ - Name
+ - Pin Usage
+ - Type
+ -
+ - Reserve
+ -
+ -
+ - S L E W
+ - R X
+ - P U - P D
+ - P U / DE N
+ - Mux Mode
+ * - `+`
+ - `+`
+ - `+`
+ - `+`
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ - 0
+ * - 222
+ - P9-39
+ - AIN0
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 224
+ - P9-40
+ - AIN1
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 226
+ - P9-37
+ - AIN2
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 228
+ - P9-38
+ - AIN3
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 230
+ - P9-33
+ - AIN4
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 232
+ - P9-36
+ - AIN5
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ * - 234
+ - P9-35
+ - AIN6
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+ - `+`
+
+
+.. _pin-usage-consideration:
+
+Pin Usage Consideration
+========================
+
+This section covers things to watch for when hooking up to certain pins
+on the expansion headers.
+
+.. _expansion-connectors-1:
+
+Expansion Connectors
+====================
+
+A combination of male and female headers is used for access to the
+expansion headers on the main board. There are three possible mounting
+configurations for the expansion headers:
+
+* **Single** -no board stacking but can be used on the top of the stack.
+* **Stacking-up** to four boards can be stacked on top of each other.
+* **Stacking with signal stealing-up** to three boards can be stacked on top of each other, but certain boards will not pass on the signals they are using to prevent signal loading or use by other cards in the stack.
+
+The following sections describe how the connectors are to be implemented
+and used for each of the different configurations.
+
+.. _non-stacking-headers-single-cape:
+
+Non-Stacking Headers-Single Cape
+=================================
+
+For non-stacking capes single configurations or where the cape can be
+the last board on the stack, the two 46 pin expansion headers use the
+same connectors. :ref:`single-expansion-connector-figure` is a picture of
+the connector. These are dual row 23 position 2.54mm x 2.54mm connectors.
+
+.. _single-expansion-connector-figure:
+
+.. figure:: media/ch08/single-expansion-connector.*
+ :width: 400px
+ :align: center
+
+ Single expansion connector
+
+The connector is typically mounted on the bottom side of the board as
+shown in :ref:`single-cape-expansion-connector-figure` . These are very
+common connectors and should be easily located. You can also use two
+single row 23 pin headers for each of the dual row headers.
+
+.. _single-cape-expansion-connector-figure:
+
+.. figure:: media/ch08/proto.*
+ :width: 400px
+ :align: center
+
+ Single cape expansion connector on BeagleBone Proto Cape with EEPROM from onlogic
+
+It is allowed to only populate the pins you need. As this is a
+non-stacking configuration, there is no need for all headers to be
+populated. This can also reduce the overall cost of the cape. This
+decision is up to the cape designer.
+
+For convenience listed in :ref:`single-cape-connectors-figure` are some possible
+choices for part numbers on this connector. They have varying pin lengths and
+some may be more suitable than others for your use. It should be noted, that the
+longer the pin and the further it is inserted into BeagleBone AI-64
+connector, the harder it will be to remove due to the tension on 92
+pins. This can be minimized by using shorter pins or removing those pins
+that are not used by your particular design. The first item in**Table
+18** is on the edge and may not be the best solution. Overhang is the
+amount of the pin that goes past the contact point of the connector on
+BeagleBone AI-64
+
+
+.. _single-cape-connectors-figure:
+
+.. list-table:: Single Cape Connectors
+ :header-rows: 1
+
+
+ * - SUPPLIER
+ - PARTNUMBER
+ - LENGTH(in)
+ - OVERHANG(in)
+ * - `Major League <http://www.mlelectronics.com/>`_
+ - TSHC-123-D-03-145-G-LF
+ - .145
+ - .004
+ * - `Major League <http://www.mlelectronics.com/>`_
+ - TSHC-123-D-03-240-G-LF
+ - .240
+ - .099
+ * - `Major League <http://www.mlelectronics.com/>`_
+ - TSHC-123-D-03-255-G-LF
+ - .255
+ - .114
+
+
+The G in the part number is a plating option. Other options may be used
+as well as long as the contact area is gold. Other possible sources are
+Sullins and Samtec for these connectors. You will need to ensure the
+depth into the connector is sufficient
+
+.. _main-expansion-headers-stacking:
+
+Main Expansion Headers-Stacking
+================================
+
+For stacking configuration, the two 46 pin expansion headers use the
+same connectors. :ref:`expansion-connector-figure` is a picture of the
+connector. These are dual row 23 position 2.54mm x 2.54mm connectors.
+
+.. _expansion-connector-figure:
+
+.. figure:: media/ch08/expansion-connector.*
+ :width: 400px
+ :align: center
+
+ Expansion Connector
+
+The connector is mounted on the top side of the board with longer tails
+to allow insertion into BeagleBone AI-64.
+:ref:`stacked-cape-expansion-connector-figure` is the
+connector configuration for the connector.
+
+.. _stacked-cape-expansion-connector-figure:
+
+.. figure:: media/ch08/can-cape.*
+ :width: 250px
+ :align: center
+
+ Stacked cape expansion connector
+
+For convenience listed in *Table 18* are some possible choices for part
+numbers on this connector. They have varying pin lengths and some may be
+more suitable than others for your use. It should be noted, that the
+longer the pin and the further it is inserted into BeagleBone AI-64
+connector, the harder it will be to remove due to the tension on 92
+pins. This can be minimized by using shorter pins. There are most likely
+other suppliers out there that will work for this connector as well. If
+anyone finds other suppliers of compatible connectors that work, let us
+know and they will be added to this document. The first item in **Table
+19** is on the edge and may not be the best solution. Overhang is the
+amount of the pin that goes past the contact point of the connector on
+BeagleBone AI-64.
+
+The third part listed in :ref:`stacked-cape-connectors-figure` will have
+insertion force issues.
+
+.. _stacked-cape-connectors-figure:
+
+.. list-table:: Stacked Cape Connectors
+ :header-rows: 1
+
+ * - SUPPLIER
+ - PARTNUMBER
+ - TAIL LENGTH(in)
+ - OVERHANG(in)
+ * - `Major League <http://www.mlelectronics.com/>`_
+ - SSHQ-123-D-06-G-LF
+ - .190
+ - 0.049
+ * - `Major League <http://www.mlelectronics.com/>`_
+ - SSHQ-123-D-08-G-LF
+ - .390
+ - 0.249
+ * - `Major League <http://www.mlelectronics.com/>`_
+ - SSHQ-123-D-10-G-LF
+ - .560
+ - 0.419
+
+There are also different plating options on each of the connectors
+above. Gold plating on the contacts is the minimum requirement. If you
+choose to use a different part number for plating or availability
+purposes, make sure you do not select the “LT†option.
+
+Other possible sources are Sullins and Samtec but make sure you select
+one that has the correct mating depth.
+
+.. _stacked-capes-wsignal-stealing:
+
+Stacked Capes w/Signal Stealing
+================================
+
+:ref:`stacked-with-signal-stealing-expansion-connector-figure` is the connector configuration for stackable capes that does
+not provide all of the signals upwards for use by other boards. This is
+useful if there is an expectation that other boards could interfere with
+the operation of your board by exposing those signals for expansion.
+This configuration consists of a combination of the stacking and
+nonstacking style connectors.
+
+.. _stacked-with-signal-stealing-expansion-connector-figure:
+
+.. figure:: media/ch08/stealing-expansion-connector.*
+ :width: 400px
+ :align: center
+
+ Stacked with signal stealing expansion connector figure
+
+.. _retention-force:
+
+Retention Force
+================
+
+The length of the pins on the expansion header has a direct relationship
+to the amount of force that is used to remove a cape from BeagleBone
+AI-64. The longer the pins extend into the connector the harder it is to
+remove. There is no rule that says that if longer pins are used, that
+the connector pins have to extend all the way into the mating connector
+on BeagleBone AI-64, but this is controlled by the user and
+therefore is hard to control. We have also found that if you use gold
+pins, while more expensive, it makes for a smoother finish which reduces
+the friction.
+
+This section will attempt to describe the tradeoffs and things to
+consider when selecting a connector and its pin length.
+
+.. _beaglebone-ai-64-female-connectors:
+
+BeagleBone AI-64 Female Connectors
+===================================
+
+:ref:`connector-pin-insertion-depth` shows the key measurements used in calculating how much the
+pin extends past the contact point on the connector, what we call
+overhang.
+
+.. _connector-pin-insertion-depth:
+
+.. figure:: media/ch08/berg-stip-insertion.*
+ :width: 400px
+ :align: center
+
+ Connector Pin Insertion Depth
+
+To calculate the amount of the pin that extends past the Point of
+Contact, use the following formula:
+
+Overhang=Total Pin Length- PCB thickness (.062) - contact point (.079)
+
+The longer the pin extends past the contact point, the more force it
+will take to insert and remove the board. Removal is a greater issue
+than the insertion.
+
+.. _signal-usage:
+
+Signal Usage
+=============
+
+Based on the pin muxing capabilities of the processor, each expansion
+pin can be configured for different functions. When in the stacking
+mode, it will be up to the user to ensure that any conflicts are
+resolved between multiple stacked cards. When stacked, the first card
+detected will be used to set the pin muxing of each pin. This will
+prevent other modes from being supported on stacked cards and may result
+in them being inoperative.
+
+In :ref:`beaglebone-ai-64-connectors` section of this document, the
+functions of the pins are defined as well as the pin muxing options.
+Refer to this section for more information on what each pin is. To
+simplify things, if you use the default name as the function for each
+pin and use those functions, it will simplify board design
+and reduce conflicts with other boards.
+
+Interoperability is up to the board suppliers and the user. This
+specification does not specify a fixed function on any pin and any pin
+can be used to the full extent of the functionality of that pin as
+enabled by the processor.
+
+*DO NOT APPLY VOLTAGE TO ANY I/O PIN WHEN POWER IS NOT SUPPLIED TO THE
+BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.*
+
+*NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES HIGH.*
+
+.. _cape-power:
+
+Cape Power
+===========
+
+This section describes the power rails for the capes and their usage.
+
+.. _main-board-power:
+
+Main Board Power
+=================
+
+The :ref:`expansion-header-voltages-table` describes the voltages from the
+main board that are available on the expansion connectors and their ratings.
+All voltages are supplied by connector**P9**. The current ratings listed are per pin.
+
+.. _expansion-header-voltages-table:
+
+
+.. list-table:: Expansion Voltages
+ :header-rows: 1
+
+
+ * - Current
+ - Name
+ - P9
+ - P9
+ - Name
+ - Current
+ * - 250mA
+ - VDD_3V3B
+ - 3
+ - 4
+ - VDD_3V3B
+ - 250mA
+ * - 1000mA
+ - VDD_5V
+ - 5
+ - 6
+ - VDD_5V
+ - 1000mA
+ * - 250mA
+ - SYS_5V
+ - 7
+ - 8
+ - SYS_5V
+ - 250mA
+
+The *VSYS_IO_3V3* rail is supplied by the LDO on BeagleBone AI-64 and
+is the primary power rail for expansion boards. If the power requirement
+for the capes exceeds the current rating, then locally generated voltage
+rail can be used. It is recommended that this rail be used to power any
+buffers or level translators that may be used.
+
+*DC_VDD_5V* is the main power supply from the DC input jack. This voltage
+is not present when the board is powered via USB. The amount of current
+supplied by this rail is dependent upon the amount of current available.
+Based on the board design, this rail is limited to 1A per pin from the
+main board.
+
+The *VSYS_5V0* rail is the main rail for the regulators on the main board.
+When powered from a DC supply or USB, this rail will be 5V. The
+available current from this rail depends on the current available from
+the USB and DC external supplies.
+
+.. _expansion-board-external-power:
+
+Expansion Board External Power
+===============================
+
+A cape can have a jack or terminals to bring in whatever voltages may be
+needed by that board. Care should be taken not to let this voltage be
+fed back into any of the expansion header pins.
+
+It is possible to provide 5V to the main board from an expansion board.
+By supplying a 5V signal into the *DC_VDD_5V* rail, the main board can be
+supplied. This voltage must not exceed 5V. You should not supply any
+voltage into any other pin of the expansion connectors. Based on the
+board design, this rail is limited to 1A per pin to BeagleBone
+AI-64.
+
+*There are several precautions that need to be taken when working with
+the expansion headers to prevent damage to the board.*
+
+1. *Do not apply any voltages to any I/O pins when the board is not powered on.*
+2. *Do not drive any external signals into the I/O pins until after the VSYS_IO_3V3 rail is up.*
+3. *Do not apply any voltages that are generated from external sources.*
+4. *If voltages are generated from the DC_VDD_5V signal, those supplies must not become active until after the VSYS_IO_3V3 rail is up.*
+5. *If you are applying signals from other boards into the expansion headers, make sure you power the board up after you power up the BeagleBone AI-64 or make the connections after power is applied on both boards.*
+
+*Powering the processor via its I/O pins can cause damage to the processor.*
+
+**TODO: Add BeagleBone AI-64 cape mechanical characteristics**
+
+.. _standard-cape-size:
+
+Standard Cape Size
+===================
+
+:ref:`cape-board-dimensions-figure` shows the outline of the standard cape. The dimensions are in inches.
+
+.. _cape-board-dimensions-figure:
+
+.. figure:: media/ch08/cape-dimension.*
+ :width: 400px
+ :align: center
+
+ Cape board dimensions
+
+A notch is provided for BeagleBone Ethernet connector to stick up higher than
+the cape when mounted. This also acts as a key function to ensure that
+the cape is oriented correctly. Space is also provided to allow access
+to the user LEDs and reset button on BeagleBone board. On BeagleBone AI-64 board
+align it with the notch on the board silkscreen.
+
+.. _extended-cape-size:
+
+Extended Cape Size
+===================
+
+Capes larger than the standard board size are also allowed. A good
+example would be the new BeagleBone AI-64 robotics cape.
+There is no practical limit to the sizes of these types of boards.
+The notch is also optional, but it is up to the supplier to ensure that the
+cape is not plugged incorrectly on BeagleBone AI-64 such that damage would
+be cause to BeagleBone AI-64. Any such damage will be the responsibility of the
+supplier of such a cape to repair. As with all capes, the EEPROM is required and
+compliance with the power requirements must be adhered to.
+
+
diff --git a/boards/beaglebone/ai-64/ch07.rst b/boards/beaglebone/ai-64/04-connectors-and-pinouts.rst
similarity index 99%
rename from boards/beaglebone/ai-64/ch07.rst
rename to boards/beaglebone/ai-64/04-connectors-and-pinouts.rst
index 6b21ceb3..e6848c1c 100644
--- a/boards/beaglebone/ai-64/ch07.rst
+++ b/boards/beaglebone/ai-64/04-connectors-and-pinouts.rst
@@ -1466,3 +1466,4 @@ P9.43-P9.46
+========+========+========+========+
| GND | GND | GND | GND |
+--------+--------+--------+--------+
+
diff --git a/boards/beaglebone/ai-64/05-demos-and-tutorials.rst b/boards/beaglebone/ai-64/05-demos-and-tutorials.rst
new file mode 100644
index 00000000..e69de29b
diff --git a/boards/beaglebone/ai-64/06-support.rst b/boards/beaglebone/ai-64/06-support.rst
new file mode 100644
index 00000000..bf4da472
--- /dev/null
+++ b/boards/beaglebone/ai-64/06-support.rst
@@ -0,0 +1,213 @@
+.. _beaglebone-ai-64-support-information:
+
+Support Information
+####################
+
+All support for this design is through BeagleBoard.org community at: link: `BeagleBoard.org forum <https://forum.beagleboard.org/>`_ .
+
+
+.. _hardware-design:
+
+Hardware Design
+------------------
+
+You can find all BeagleBone AI-64 hardware files `here <https://git.beagleboard.org/beagleboard/beaglebone-ai-64>`_ under the `hw` folder.
+
+
+.. _software-updates:
+
+Software Updates
+-----------------
+
+Follow instructions below to download the latest image for your BeagleBone AI-64:
+
+1. Go to `BeagleBoard.org distro <https://www.beagleboard.org/distros>`_ page.
+2. :ref:`filter-software-distribution-AI-64` from dropdown and download the image.
+
+.. _filter-software-distribution-AI-64:
+
+.. figure:: images/ch11/distros.png
+ :align: center
+ :alt: Filter Software Distributions for BeagleBone AI-64
+
+ Filter Software Distributions for BeagleBone AI-64
+
+.. tip::
+ You can follow the :ref:`flash-latest-image` guide for more information on
+ flashing the downloaded image to your board.
+
+To see what SW revision is loaded into the eMMC check `/etc/dogtag`.
+It should look something like as shown below,
+
+```
+root@BeagleBone:~# cat /etc/dogtag
+BeagleBoard.org Debian Bullseye Xfce Image 2022-01-14
+```
+
+.. _rma-support:
+
+RMA Support
+-------------------------------------
+
+If you feel your board is defective or has issues, request an Return Merchandise Application (RMA) by filling out the form at http://beagleboard.org/support/rma . You will need the serial number and revision of the board. The serial numbers and revisions keep moving. Different boards can have different locations depending on when they were made. The following figures show the three locations of the serial and revision number.
+
+.. _trouble-shooting-video-output-issues:
+
+Troubleshooting video output issues
+-------------------------------------
+
+.. warning::
+
+ When connecting to an HDMI monitor, make sure your miniDP adapter is *active*. A *passive* adapter will not work. See :ref:`display-adapters-figure`.
+
+
+.. _getting-help:
+
+Getting Help
+*************
+
+If you need some up to date troubleshooting techniques, you can post your queries on link: `BeagleBoard.org forum <https://forum.beagleboard.org/>`_
+
+.. _bbai64-Change-history:
+
+Change History
+###################
+
+This section describes the change history of this document and board. Document changes are not always a result of a board change. A board change will always result in a document change.
+
+.. _bbai64-document-change-history:
+
+Document Change History
+-----------------------------------------
+
+This table seeks to keep track of major revision cycles in the documentation. Moving forward, we'll seek to align these version numbers across all of the various documentation.
+
+.. _change-history-table, Change History:
+
+.. list-table:: Table 1: Change History
+ :header-rows: 1
+
+ * - Rev
+ - Changes
+ - Date
+ - By
+ * - 0.0.1
+ - AI-64 initial prototype
+ - September 2021
+ - James Anderson
+ * - 0.0.2
+ - AI-64 final prototype
+ - December 2021
+ - James Anderson
+ * - 0.0.3
+ - AI-64 initial production release
+ - June 9, 2022
+ - Deepak Khatri and Jason Kridner
+
+.. _board-changes:
+
+Board Changes
+------------------
+
+Be sure to check the board revision history in the schematic file in the `BeagleBone AI-64 git repository <https://git.beagleboard.org/beagleboard/beaglebone-ai-64>`_ . Also check the `issues list <https://git.beagleboard.org/beagleboard/beaglebone-ai-64/-/issues>`_ .
+
+.. _rev-B:
+
+Rev B
+*********
+We are starting with revision B based on this being an update to the BeagleBone Black AI. However, because this board ended up being so different, we've decided to name it BeagleBone AI-64, rather than simply a new revision. This refers to the Seeed release on 21 Dec 2021 of "BeagleBone AI-64_SCH_Rev B_211221". This is the initial production release.
+
+.. _BeagleBone-AI-64-Mechanical:
+
+BeagleBone AI-64 Mechanical
+#############################
+
+.. _dimensions-and-weight:
+
+Dimensions and Weight
+------------------------------------
+
+Size: 102.5 x 80 (4" x 3.15")
+
+Max height: #TODO#
+
+PCB Layers: #TODO#
+
+PCB thickness: 2mm (0.08")
+
+RoHS Compliant: Yes
+
+Weight: 192gm
+
+.. _silkscreen-and-component-locations:
+
+Silkscreen and Component Locations
+------------------------------------
+
+.. figure:: media/ch09/board-dimensions.*
+ :width: 400px
+ :align: center
+
+ Board Dimensions
+
+.. figure:: media/ch09/top-silkscreen.*
+ :width: 400px
+ :align: center
+
+ Top silkscreen
+
+.. figure:: media/ch09/bottom-silkscreen.*
+ :width: 400px
+ :align: center
+
+ Bottom silkscreen
+
+
+.. _bbai64-pictures:
+
+Pictures
+##########
+
+.. figure:: media/ch10/front.*
+ :width: 400px
+ :align: center
+
+ BeagleBone AI-64 front
+
+.. figure:: media/ch10/back.*
+ :width: 400px
+ :align: center
+
+ BeagleBone AI-64 back
+
+.. figure:: media/ch10/back-heatsink.*
+ :width: 400px
+ :align: center
+
+ BeagleBone AI-64 back with heatsink
+
+.. figure:: media/bbai64-45-front.*
+ :width: 400px
+ :align: center
+
+ BeagleBone AI-64 front at 45° angle
+
+.. figure:: media/ch10/45-back.*
+ :width: 400px
+ :align: center
+
+ BeagleBone AI-64 back at 45° angle
+
+.. figure:: media/ch10/45-back-heatsink.*
+ :width: 400px
+ :align: center
+
+ BeagleBone AI-64 back with heatsink at 45° angle
+
+.. figure:: media/ch10/feature.*
+ :width: 400px
+ :align: center
+
+ BeagleBone AI-64 ports
+
+
diff --git a/boards/beaglebone/ai-64/ch01.rst b/boards/beaglebone/ai-64/ch01.rst
deleted file mode 100644
index 9493ac71..00000000
--- a/boards/beaglebone/ai-64/ch01.rst
+++ /dev/null
@@ -1,18 +0,0 @@
-.. _bbai64-introduction:
-
-Introduction
-###############
-
-This document is the *System Reference Manual* for BeagleBone AI-64
-and covers its use and design. The board will primarily be referred to
-in the remainder of this document simply as the board, although it may
-also be referred to as AI-64 or BeagleBone AI-64 as a reminder.
-
-This design is subject to change without notice as we will work to keep
-improving the design as the product matures based on feedback and
-experience. Software updates will be frequent and will be independent of
-the hardware revisions and as such not result in a change in the
-revision number.
-
-Make sure you frequently check the `BeagleBone AI-64 git repository <https://git.beagleboard.org/beagleboard/beaglebone-ai-64/>`_ for the most up to date support documents.
-
diff --git a/boards/beaglebone/ai-64/ch02.rst b/boards/beaglebone/ai-64/ch02.rst
deleted file mode 100644
index 5599fb6b..00000000
--- a/boards/beaglebone/ai-64/ch02.rst
+++ /dev/null
@@ -1,49 +0,0 @@
-.. _bbai64-Change-history:
-
-Change History
-###################
-
-This section describes the change history of this document and board. Document changes are not always a result of a board change. A board change will always result in a document change.
-
-.. _bbai64-document-change-history:
-
-Document Change History
------------------------------------------
-
-This table seeks to keep track of major revision cycles in the documentation. Moving forward, we'll seek to align these version numbers across all of the various documentation.
-
-.. _change-history-table, Change History:
-
-.. list-table:: Table 1: Change History
- :header-rows: 1
-
- * - Rev
- - Changes
- - Date
- - By
- * - 0.0.1
- - AI-64 initial prototype
- - September 2021
- - James Anderson
- * - 0.0.2
- - AI-64 final prototype
- - December 2021
- - James Anderson
- * - 0.0.3
- - AI-64 initial production release
- - June 9, 2022
- - Deepak Khatri and Jason Kridner
-
-.. _board-changes:
-
-Board Changes
-------------------
-
-Be sure to check the board revision history in the schematic file in the `BeagleBone AI-64 git repository <https://git.beagleboard.org/beagleboard/beaglebone-ai-64>`_ . Also check the `issues list <https://git.beagleboard.org/beagleboard/beaglebone-ai-64/-/issues>`_ .
-
-.. _rev-B:
-
-Rev B
-*********
-We are starting with revision B based on this being an update to the BeagleBone Black AI. However, because this board ended up being so different, we've decided to name it BeagleBone AI-64, rather than simply a new revision. This refers to the Seeed release on 21 Dec 2021 of "BeagleBone AI-64_SCH_Rev B_211221". This is the initial production release.
-
diff --git a/boards/beaglebone/ai-64/ch04.rst b/boards/beaglebone/ai-64/ch04.rst
deleted file mode 100644
index 503d6ece..00000000
--- a/boards/beaglebone/ai-64/ch04.rst
+++ /dev/null
@@ -1,201 +0,0 @@
-.. _beaglebone-ai-64-overview:
-
-BeagleBone AI-64 Overview
-###############################
-
-BeagleBone AI-64 is the latest addition to BeagleBoard.org family and like its predecessors, is designed to address the open-source Community, early adopters, and anyone interested in a low cost 64-bit Dual Arm® Cortex®-A72 processor based Single Board Computer (SBC).
-
-It has been equipped with a minimum set of features to allow the user to
-experience the power of the processor and is not intended as a full
-development platform as many of the features and interfaces supplied by
-the processor are not accessible from BeagleBone AI-64 via onboard
-support of some interfaces. It is not a complete product designed to do
-any particular function. It is a foundation for experimentation and
-learning how to program the processor and to access the peripherals by
-the creation of your own software and hardware.
-
-It also offers access to many of the interfaces and allows for the use
-of add-on boards called capes, to add many different combinations of
-features. A user may also develop their own board or add their own
-circuitry.
-
-BeagleBone AI-64 is manufactured and warranted by partners listed at https://beagleboard.org/logo for the benefit of the community and its supporters including the current BeagleBoard.org Foundation board members
-
-* Jason Kridner, principal of JK Embedded Consulting an independent contractor and architect for new Beagle designs.
-* Drew Fustini, independent Linux developer
-* Robert Nelson, applications engineer at Digi-Key
-* Mark Yoder, professor at Rose-Hulman Institute of Technology
-* Kathy Giori, product engineer at ZEDEDA
-
-See `bbb.io/about <https://beagleboard.org/about>`_
-
-BeagleBone AI-64 has been designed by Seeed Studio (Seeed Development Limited) under guidance from BeagleBoard.org Foundation.
-
-.. _beaglebone-compatibilityd:
-
-BeagleBone Compatibility
---------------------------------
-
-The board is intended to provide functionality well beyond BeagleBone Black or BeagleBone AI, while still providing compatibility with BeagleBone Black's expansion headers as
-much as possible. There are several significant differences between the three designs.
-
-.. _beaglebone-comparison-table, BeagleBone Comparisond:
-
-.. list-table:: Table: BeagleBone Compatibility
- :header-rows: 1
-
- * - Feature
- - AI-64
- - AI
- - Black
- * - SoC
- - TDA4VM
- - AM5729
- - AM3358
- * - Arm CPU
- - Cortex-A72 (64-bit)
- - Cortex-A15 (32-bit)
- - Cortex-A8 (32-bit)
- * - Arm cores/MHz
- - 2x 2GHz
- - 2x 1.5GHz
- - 1x 1GHz
- * - RAM
- - 4GB
- - 1GB
- - 512MB
- * - eMMC flash
- - 16GB
- - 16GB
- - 4GB
- * - Size
- - 4" x 3.1"
- - 3.4" x 2.1"
- - .4" x 2.1"
- * - Display
- - miniDP + DSI
- - microHDMI
- - microHDMI
- * - USB host (Type-A)
- - 2x 5Gbps
- - 1x 480Mbps
- - 1x 480Mbps
- * - USB dual-role
- - Type-C 5Gbps
- - Type-C 5Gbps
- - mini-AB 480Mbps
- * - Ethernet
- - 10/100/1000M
- - 10/100/1000M
- - 10/100M
- * - M.2
- - E-key
- - `-`
- - `-`
- * - WiFi/ Bluetooth
- - `-`
- - AzureWave AW‑CM256SM
- - `-`
-
-.. todo::
-
- add cape compatibility details
-
-
-.. _beaglebone-ai-64-features-and-specificationd:
-
-BeagleBone AI-64 Features and Specification
------------------------------------------------
-
-This section covers the specifications and features of the board and provides a high level description of the major components and interfaces that make up the board.
-
-.. _ai64-features,BeagleBone AI-64 features tabled:
-
-.. list-table:: Table: BeagleBone AI-64 Features and Specification
- :header-rows: 1
-
- * -
- - Feature
- * - **Processor**
- - Texas Instruments TDA4VM
- * - **Graphics Engine**
- - PowerVR® Series8XE GE8430
- * - **SDRAM Memory**
- - LPDDR4 3.2GHz (4GB) Kingston Q3222PM1WDGTK-U
- * - **Onboard Flash**
- - eMMC (16GB) Kingston EMMC16G-TB29-PZ90
- * - **PMIC**
- - TPS65941213 and TPS65941111 PMICs regulator and one additional LDO.
- * - **Debug Support**
- - 2x 3 pin 3.3V TTL header
- 1. WKUP_UART0: Wake-up domain serial port
- 2. UART0: Main domain serial port
-
- 10-pin JTAG TAG-CONNECT footprint
- * - **Power Source**
- - USB C or DC Jack (5V, >3A)
- * - **PCB**
- - 4†x 3.1â€
- * - **Indicators**
- - 1-Power, 5-User Controllable LEDs
- * - **USB-3.0 Client Port**
- - Access to USB0, SuperSpeed, dual-role mode via USB-C (no power output)
- * - **USB-3.0 Host Port**
- - TUSB8041 4-port SuperSpeed hub on USB1, 2xType A Socket, up-to 2.8A total, depending on power input
- * - **Ethernet**
- - Gigabit, RJ45, link indicator, speed indicator
- * - **SD/MMC Connector**
- - microSD , 1.8/3.3V
- * - **User Input**
- -
- 1. Reset Button
- 2. Boot Button
- 3. Power Button
- * - **Video Out**
- - miniDP
- * - **Audio**
- - via miniDP (stereo)
- * - **Weight**
- - 192gm (with heatsink)
- * - **Power**
- - Refer to :ref:`main-board-power` section
-
-.. _board-component-locations:
-
-Board Component Locations
---------------------------------
-
-This section describes the key components on the board. It provides information on their location and function. Familiarize yourself with the various components on the board.
-
-.. _board-components:
-
-Board components
----------------------
-
-:ref:`board-components-figure` below shows the locations of the connectors, LEDs, and switches on the PCB layout of the board.
-
-.. _board-components-figure:
-
-.. figure:: media/ch04/components.*
- :width: 400px
- :align: center
- :caption: BeagleBone AI-64 board components
-
-* **DC Power** is the main DC input that accepts 5V power.
-* **Power Button** alerts the processor to initiate the power down sequence and is used to power down the board.
-* **GigaBit Ethernet** is the connection to the LAN.
-* **Serial Debug ports** WKUP_UART0 for early boot from the management MCU and UART0 is for the main processor.
-* **USB Client** is a USB-C connection to a PC that can also power the board.
-* **BOOT switch** can be used to force a boot from the microSD card if the power is cycled on the board, removing power and reapplying the power to the board.
-* There are five green **LEDs** that can be used by the user.
-* **Reset Button** allows the user to reset the processor.
-* **microSD** slot is where a microSD card can be installed.
-* **miniDP** connector is where the display is connected to.
-* **USB Host** can be connected different USB interfaces such as Wi-Fi, Bluetooth, Keyboard, etc.
-
-On bottom side we have,
-
-* **TI TDA4VM** processor.
-* **4GB LPDDR4** Dual Data Rate RAM memory.
-* **Ethernet PHY** physical interface to the network.
-* **eMMC** onboard MMC chip that holds up to 16GB of data.
diff --git a/boards/beaglebone/ai-64/ch05.rst b/boards/beaglebone/ai-64/ch05.rst
deleted file mode 100644
index b1274454..00000000
--- a/boards/beaglebone/ai-64/ch05.rst
+++ /dev/null
@@ -1,315 +0,0 @@
-.. _beaglebone-ai-64-high-level-specification:
-
-BeagleBone AI-64 High Level Specification
-##############################################
-
-:ref:`BeagleBone_AI-64-block-diagram` below shows the high level block diagram of BeagleBone AI-64 board surrounding TDA4VM SoC.
-
-.. _BeagleBone_AI-64-block-diagram:
-
-.. figure:: media/ch05/board-block-diagram.*
- :width: 400px
- :align: center
- :caption: BeagleBone AI-64 Key Components
-
-.. _processor:
-
-Processor
-----------------
-
-BeagleBone AI-64 uses TI J721E-family `TDA4VM <https://www.ti.com/product/TDA4VM>`_ system-on-chip (SoC) which is part of the K3 Multicore SoC architecture platform and it is targeted for the reliability and low-latency needs of the automotive market provide for a great general purpose platform suitable for industrial automation, mobile robotics, building automation and numerous hobby projects.
-
-The SoC designed as a low power, high performance and highly integrated device architecture, adding significant enhancement on processing power, graphics capability, video and imaging processing, virtualization and coherent memory support. In addition, these SoCs support state of the art security and functional safety features. For the remaining of this section device, SoC, and processor will be used interchangeably.
-
-**Some of the main distinguished characteristics of the device are:**
-
-* 64-bit architecture with virtualization and coherent memory support, which leverages full processing capability of 64-bit Arm® Cortex®-A72
-* Fully programmable industrial communication subsystems to enable future-proof designs for customers that need to adopt the new Gigabit Time-sensitive Networks (TSN) standards, but still need full support on legacy protocols and continuous system optimization over the product deployment
-* Integration of vision hardware processing accelerators to facilitate extensive processing requirements in low power budget for automotive ADAS and machine vision applications
-* Integration of a general-purpose microcontroller unit (MCU) with a dual Arm® Cortex®-R5F MCU subsystem, available for general purpose use as two cores or in lockstep, intended to help customers achieve functional safety goals for their end products
-* Integration of a next-generation fixed and floating-point C71x Digital Signal Processor (DSP) that significantly boosts power over a broad range of general signal processing tasks for both general applications and automotive functions which also incorporates advanced techniques to improve control code efficiency and ease of programming such as branch prediction, protected pipeline, precise exception and virtual memory management
-* Tightly coupled Matrix Multiplication Accelerator (MMA) that extends the C71x DSP architecture's scalar and vector facilities enabling deep learning and enhance vision, analytics and wide range of general applications. The achieved total TOPS (Tera Operations Per Second) performance significantly differentiates the device for single board computer in machine vision and deep learning applications
-* Key display features including flexibility to interface with different panel types (eDP, DSI, DPI) with multi-layer hardware composition
-* Integration of hardware features that help applications to achieve functional safety mechanisms
-* Robust security architecture with sandboxed DMSC controller managing all secure configurations with high performance client-server messaging scheme between secure DMSC and all cores
-* Simplified solution for power supply management, enabling lower cost system solution (on-die bias LDOs and power good comparators for minimal power sequencing requirements consistent with low cost supply design)
-
-**The device is composed of the following main subsystems, across different domains of the SoC, among others:**
-
-* One dual-core 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz and up to 24K DMIPS (Dhrystone Million Instructions per Second)
-* Up to three Microcontroller Units (MCU), based on dual-core Arm Cortex-R5F processor running at up to 1.0 GHz, up to 12K DMIPS
-* Up to two TMS320C66x DSP CorePac modules running at up to 1.35 GHz, up to 40 GFLOPS
-* One C71x floating point, vector DSP running at up to 1.0 GHz, up to 80 GFLOPS
-* One deep-learning MMA, up to 8 TOPS (8b) at 1.0 GHz
-* Up to two gigabit dual-core Programmable Real-Time Unit and Industrial Communication Subsystems (PRU_ICSSG)
-* Two Navigator Subsystems (NAVSS) for data movement and control
-* One multi-pipeline Display Subsystem (DSS) with one MIPI® Display Serial Interface Controller (DSI) and shared MIPI D-PHY Transmitter (DPHY_TX), one Embedded DisplayPort Transmitter (EDP) with shared Serializer/Deserializer (SERDES), and two MIPI Display Pixel Interface (DPI) ports
-* Two Camera Streaming Interface Receivers (CSI_RX_IF) with dedicated MIPI D-PHYs (DPHY_RX)
-* One Camera Streaming Interface Transmitter (CSI_TX_IF) with MIPI D-PHY Transmitter (DPHY_TX) shared with DSI
-* One Vision Processing Accelerator (VPAC) with image signal processor
-* One Depth and Motion Processing Accelerator (DMPAC)
-* One dual-core multi-standard HD Video Decoder (DECODER)
-* One dual-core multi-standard HD Video Encoder (ENCODER)
-* One Graphics Processing Unit (GPU)
-* One Device Management and Security Controller (DMSC)
-
-**The device provides a rich set of peripherals such as:**
-
-* General connectivity peripherals, including:
-
- * ``Two 12-bit general purpose Analog-to-Digital Converters (ADC)``
- * ``Ten Inter-Integrated Circuit (I2C) interfaces``
- * ``Three Improved Inter-Integrated Circuit (I3C) controllers``
- * ``Eleven master/slave Multichannel Serial Peripheral Interfaces (MCSPI)``
- * ``Twelve configurable Universal Asynchronous Receiver/Transmitter (UART) interfaces``
- * ``Ten General-Purpose Input/Output (GPIO) modules``
-
-* High-speed interfaces, including:
-
- * ``Two Gigabit Ethernet Switch (CPSW) modules``
- * ``Two Dual-Role-Device (DRD) Universal Serial Bus Subsystems (USBSS) with integrated PHY``
- * ``Four Peripheral Component Interconnect express (PCIe) Gen3 subsystems``
-
-* Flash memory interfaces, including:
-
- * ``One Octal SPI (OSPI) interface and one Quad SPI (QSPI) or one QSPI and one HyperBus^TM^``
- * ``One General Purpose Memory Controller (GPMC) with Error Location Module (ELM) and 8- or 16-bit-wide data bus width (supports parallel NOR or NAND FLASH devices)``
- * ``Three Multimedia Card/Secure Digital (MMCSD) controllers``
- * ``One Universal Flash Storage (UFS) interface``
-
-* Industrial and control interfaces, including:
-
- * ``Sixteen Controller Area Network (MCAN) interfaces with flexible data rate support``
- * ``Three Enhanced Capture (ECAP) modules``
- * ``Six Enhanced Pulse-Width Modulation (EPWM) subsystems``
- * ``Three Enhanced Quadrature Encoder Pulse (EQEP) modules``
-
-* Audio peripherals, including:
-
- * ``One Audio Tracking Logic (ATL)``
- * ``Twelve Multichannel Audio Serial Port (MCASP) modules supporting up to 16 channels with independent TX/RX clock/sync domain``
-
-* One Video Processing Front End (VPFE) interface module
-
-**The device also integrates:**
-
-* Power distribution, reset controls and clock management components
-
-* Power-management techniques for device power consumption minimization:
-
- * ``Adaptive Voltage Scaling (AVS)``
- * ``Dynamic Frequency Scaling (DFS)``
- * ``Gated clocks``
- * ``Multiple voltage domains``
- * ``Independently controlled power domains for major modules``
- * ``Voltage and Temperature Management (VTM) module``
- * ``Power-on Reset Generators (PRG)``
- * ``Power Sleep Controllers (PSC)``
-
-* Optimized interconnect (CBASS) architecture to enable latency-critical real time network and IO applications
-
-* Control modules (CTRL_MMRs) mainly associated with device top-level configurations such as:
-
- * ``IO Pad and pin multiplexing configuration``
- * ``PLL control and associated High-Speed Dividers (HSDIV)``
- * ``Clock selection``
- * ``Analog function controls``
-
-* Multicore Shared Memory Controller (MSMC)
-* DDR Subsystem (DDRSS) with Error Correcting Code (ECC), supporting LPDDR4
-* 1KB RAM with ECC support for C71x boot vectors
-* 2KB RAM with ECC support for A72 and R5F boot vectors
-* 512KB On-Chip SRAM protected by ECC
-* One Global Time Counter (GTC) module
-* Thirty 32-bit counter timers with compare and capture modes
-* Debug and trace capabilities
-
-**The device includes different modules for functional safety requirements support:**
-
-* MCU island with dual lock step Arm Cortex-R5F
-* Safety enabled interconnect with implemented features to help with Freedom From Interference (FFI)
-* Twelve Real Time Interrupt (RTI) modules with Windowed Watchdog Timer (WWDT) functionality to monitor processor cores
-* Sixteen Dual-Clock Comparators (DCC) to monitor clocking sources during run-time
-* Three Error Signaling Modules (ESM) to enable error monitoring
-* Temperature monitoring sensors
-* ECC on all critical memories
-* Dedicated hardware Memory Cyclic Redundancy Check (MCRC) blocks
-
-**The device supports the following main security functionalities among others:**
-
-* Secure Boot Management
-* Public Key Accelerator (PKA) for large vector math operation
-* Cryptographic acceleration (AES, 3DES, MD5, SHA1, SHA2-224, 256, 512 operation)
-* Trusted Execution Environment (TEE)
-* Secure storage support
-* On-the-fly encryption and authentication support for OSPI interface
-
-The device is partitioned into three functional domains as shown in :ref:`soc-block-diagram`, each containing specific processing cores and peripherals:
-
-* Wake-up (WKUP) domain
-* Microcontroller (MCU) domain with one of the dual Cortex-R5 cluster
-* MAIN domain
-
-.. _soc-block-diagram:
-
-.. figure:: media/ch05/soc-block-diagram.*
- :width: 400px
- :align: center
- :caption: Device Top-level Block Diagram
-
-.. _memory:
-
-Memory
-------------
-
-Described in the following sections are the three memory devices found on the board.
-
-.. _mb-ddr4l:
-
-4GB LPDDR4
-************
-
-A single (1024M x 16bits x 2channels) LPDDR4 4Gb memory device is used. The memory used is:
-
-* Kingston Q3222PM1WDGTK-U
-
-.. _kb-eeprom:
-
-4Kb EEPROM
-*********************************
-
-A single 4Kb EEPROM (24FC04HT-I/OT) is provided on I2C0 that holds the board information. This information includes board name, serial number, and revision information.
-
-.. _gb-embedded-mmc:
-
-16GB Embedded MMC
-*********************************
-
-A single 16GB embedded MMC (eMMC) device is on the board. The device
-connects to the MMC1 port of the processor, allowing for 8bit wide
-access. Default boot mode for the board will be MMC1 with an option to
-change it to MMC0, the SD card slot, for booting from the SD card as a
-result of removing and reapplying the power to the board. Simply
-pressing the reset button will not change the boot mode. MMC0 cannot be
-used in 8Bit mode because the lower data pins are located on the pins
-used by the Ethernet port. This does not interfere with SD card
-operation but it does make it unsuitable for use as an eMMC port if the
-8 bit feature is needed.
-
-.. _microsd-connector:
-
-MicroSD Connector
-*********************************
-
-The board is equipped with a single microSD connector to act as the
-secondary boot source for the board and, if selected as such, can be the
-primary boot source. The connector will support larger capacity microSD
-cards. The microSD card is not provided with the board. Booting from
-MMC0 will be used to flash the eMMC in the production environment or can
-be used by the user to update the SW as needed.
-
-.. _boot-modes:
-
-Boot Modes
-*************
-
-As mentioned earlier, there are two boot modes:
-
-* **eMMC Boot:** This is the default boot mode and will allow for the fastest boot time and will enable the board to boot out of the box using the pre-flashed OS image without having to purchase an microSD card or an microSD card writer.
-* **SD Boot:** This mode will boot from the microSD slot. This mode can be used to override what is on the eMMC device and can be used to program the eMMC when used in the manufacturing process or for field updates.
-
-.. todo::
-
- This section needs more work and references to greater detail. Other boot modes are possible.
- Software to support USB and serial boot modes is not provided by beagleboard.org._Please contact TI for support of this feature.
-
-
-A switch is provided to allow switching between the modes.
-
-* Holding the boot switch down during a removal and reapplication of power without a microSD card inserted will force the boot source to be the USB port and if nothing is detected on the USB client port, it will go to the serial port for download.
-* Without holding the switch, the board will boot try to boot from the eMMC. If it is empty, then it will try booting from the microSD slot, followed by the serial port, and then the USB port.
-* If you hold the boot switch down during the removal and reapplication of power to the board, and you have a microSD card inserted with a bootable image, the board will boot from the microSD card.
-
-.. note ::
-
- Pressing the RESET button on the board will NOT result in a change of the boot mode. You MUST remove power and reapply power to change the boot mode. The boot pins are sampled during power on reset from the PMIC to the processor.The reset button on the board is a warm reset only and will not force a boot mode change.
-
-.. _power-management:
-
-Power Management
--------------------
-
-The *TPS65941213 and TPS65941111* power management device is used along with a separate LDO to provide power to the system.
-
-.. _pc-usb-interface:
-
-PC USB Interface
----------------------
-
-The board has a USB type-C connector that connects to USB0 port of the processor.
-
-.. _serial-debug-ports:
-
-Serial Debug Ports
-------------------------------------
-
-Two serial debug ports are provided on board via 3pin micro headers,
-
-1. WKUP_UART0: Wake-up domain serial port
-2. UART0: Main domain serial port
-
-
-In order to use the interfaces a `3pin micro to 6pin dupont adaptor header <https://uk.farnell.com/element14/1103004000156/beaglebone-ai-serials-cable/dp/3291081>`_ is required with a 6 pin USB to TTL adapter. The header is compatible with the one provided by FTDI and can be purchased for about $$12 to $$20 from various sources. Signals supported are TX and RX. None of the handshake signals are supported.
-
-.. _usb1-host-port:
-
-USB1 Host Port
-------------------
-
-On the board is a single USB Type A female connector with full LS/FS/HS
-Host support that connects to USB1 on the processor. The port can
-provide power on/off control and up to 1.5A of current at 5V. Under USB
-power, the board will not be able to supply the full 1.5A, but should
-be sufficient to supply enough current for a lower power USB device
-supplying power between 50 to 100mA.
-
-.. _power-sources:
-
-Power Sources
-------------------------------------
-
-The board can be powered from two different sources:
-
-* A 5V > 3A power supply plugged into the barrel jack.
-* A wall adaptor with 5V > 3A output power.
-
-The power supply is not provided with the board but can be easily
-obtained from numerous sources. A 5V > 3A supply is mandatory to have with
-the board, but if there is a cape plugged into the board or you have a power
-hungry device or hub plugged into the host port, then more current may
-needed from the DC supply.
-
-.. _reset-button:
-
-Reset Button
-------------------------------------
-
-When pressed and released, causes a reset of the board.
-
-.. _power-button:
-
-Power Button
-------------------------------------
-
-This button takes advantage of the input to the PMIC for
-power down features.
-
-.. _indicators:
-
-Indicators
-------------------------------------
-
-There are a total of six green LEDs on the board.
-
-* One green power LED indicates that power is applied and the power management IC is up.
-* Five blue LEDs that can be controlled via the SW by setting GPIO pins.
diff --git a/boards/beaglebone/ai-64/ch06.rst b/boards/beaglebone/ai-64/ch06.rst
deleted file mode 100644
index cbb7ade9..00000000
--- a/boards/beaglebone/ai-64/ch06.rst
+++ /dev/null
@@ -1,1707 +0,0 @@
-:orphan:
-
-.. _bbai64-detailed-hardware-design:
-
-Detailed Hardware Design
-#########################
-
-This section provides a detailed description of the Hardware design.
-This can be useful for interfacing, writing drivers, or using it to help
-modify specifics of your own design.
-
-:ref:`bbai-64-block-diagram-ch06` below is the high level block diagram of the board. For those who may be concerned, It is the same figure as shown in :ref:`beaglebone-ai-64-high-level-specification`. It is placed here again for convenience so it is closer to the topics to follow.
-
-.. _bbai-64-block-diagram-ch06:
-
-.. figure:: media/ch05/board-block-diagram.*
- :width: 400px
- :align: center
- :alt: Fig: BeagleBone AI-64 Key Components
-
- Fig: BeagleBone AI-64 Key Components
-
-.. _power-section:
-
-Power Section
------------------------------------
-
-:ref:`power-flow-diagram` shows the high level block diagram of the power section of the board.
-
-.. _power-flow-diagram,High level power block diagram:
-
-.. figure:: media/ch06/power.*
- :width: 400px
- :align: center
- :alt: Fig: High level power block diagram
-
- Fig: High level power block diagram
-
-This section describes the power section of the design and all the
-functions performed by the *TPS65941213 and TPS65941111*.
-
-.. todo::
-
- The above image does not represent this board. It has a Pi Header.
-
-.. _TPS65941213-and-TPS65941111-pmic:
-
-TPS65941213 and TPS65941111 PMIC
-*********************************************
-
-The main Power Management IC (PMIC) in the system is the *TPS65941213 and TPS65941111*
-which is a single chip power management IC consisting of a linear
-dual-input power path, three step-down converters, and four LDOs. LDO
-stands for Low Drop Out. If you want to know more about an LDO, you can
-go to `http://en.wikipedia.org/wiki/Low-dropout_regulator <http://en.wikipedia.org/wiki/Low-dropout_regulator>`_ .
-
-If you want to learn more about step-down converters, you can go to `_http://en.wikipedia.org/wiki/DC-to-DC_converter <http://en.wikipedia.org/wiki/DC-to-DC_converter>`_ .
-
-The system is supplied by a USB port or DC adapter. Three
-high-efficiency 2.25MHz step-down converters are targeted at providing
-the core voltage, MPU, and memory voltage for the board.
-
-The step-down converters enter a low power mode at light load for
-maximum efficiency across the widest possible range of load currents.
-For low-noise applications the devices can be forced into fixed
-frequency PWM using the I2C interface. The step-down converters allow
-the use of small inductors and capacitors to achieve a small footprint
-solution size.
-
-LDO1 and LDO2 are intended to support system standby mode. In normal
-operation, they can support up to 100mA each. LDO3 and LDO4 can support
-up to 285mA each.
-
-By default only LDO1 is always ON but any rail can be configured to
-remain up in SLEEP state. In particular the DCDC converters can remain
-up in a low-power PFM mode to support processor suspend mode. The
-*TPS65941213 and TPS65941111* offers flexible power-up and power-down sequencing and
-several house-keeping functions such as power-good output, pushbutton
-monitor, hardware reset function and temperature sensor to protect the
-battery.
-
-See the :ref:`TPS6594-Q1-block-diagram` shown below for high level details
-for *TPS65941213 and TPS65941111*, for more information on the, refer to https://www.ti.com/product/TPS6594-Q1 Texas instruments product page.
-
-.. _TPS6594-Q1-block-diagram:
-
-.. figure:: images/ch06/TPS6594-Q1.*
- :width: 400px
- :align: center
- :alt: Fig: TPS6594-Q1 block diagram
-
- Fig: TPS6594-Q1 block diagram
-
-.. _pmic-a-diagram,PMIC-A TPS65941213 circuit:
-
-.. figure:: images/ch06/pmic-a.*
- :width: 400px
- :align: center
- :alt: Fig: PMIC-B TPS65941213 circuit
-
- Fig: PMIC-B TPS65941213 circuit
-
-.. _pmic-b-diagram,PMIC-B TPS65941111 circuit:
-
-.. figure:: images/ch06/pmic-b.*
- :width: 400px
- :align: center
- :alt: Fig: PMIC-B TPS65941111 circuit
-
- Fig: PMIC-B TPS65941111 circuit
-
-.. _dc-input:
-
-DC Input
-***********
-
-:ref:`figure-23` below shows how the DC input is connected to the **TPS65941213 and TPS65941111**.
-
-.. _figure-23,Figure 23:
-
-.. figure:: media/image38.*
- :width: 400px
- :align: center
- :alt: Fig: TPS65217 DC Connection
-
- Fig: TPS65217 DC Connection
-
-A 5VDC supply can be used to provide power to the board. The power
-supply current depends on how many and what type of add-on boards are
-connected to the board. For typical use, a 5VDC supply rated at 1A
-should be sufficient. If heavier use of the expansion headers or USB
-host port is expected, then a higher current supply will be required.
-
-The connector used is a 2.1MM center positive x 5.5mm outer barrel. The
-5VDC rail is connected to the expansion header. It is possible to power
-the board via the expansion headers from an add-on card. The 5VDC is
-also available for use by the add-on cards when the power is supplied by
-the 5VDC jack on the board.
-
-.. _usb-power:
-
-USB Power
-*************
-
-The board can also be powered from the USB port. A typical USB 3.0 port is
-limited to 900mA. When powering from the USB port, the VDD_5V rail
-is not provided to the expansion headers, so capes that require the 5V
-rail to supply the cape direct, bypassing the *TPS65941213 and TPS65941111*, will not have
-that rail available for use. The 5VDC supply from the USB port is
-provided on the SYS_5V, the one that comes from the **TPS65941213 and TPS65941111**, rail
-of the expansion header for use by a cape. :ref:`bbai64-usb-power-connections` is the connection
-of the USB power input on the PMIC.
-
-.. _bbai64-usb-power-connections:
-
-.. figure:: media/USB-Connection.*
- :width: 400px
- :align: center
- :caption: USB Power Connection
-
-.. _power-selection:
-
-Power Selection
-*********************************************
-
-The selection of either the 5VDC or the USB as the power source is
-handled internally to the *TPS65941213 and TPS65941111* and automatically switches to 5VDC
-power if both are connected. SW can change the power configuration via
-the I2C interface from the processor. In addition, the SW can read
-the *TPS65941213 and TPS65941111* and determine if the board is running on the 5VDC input
-or the USB input. This can be beneficial to know the capability of the
-board to supply current for things like operating frequency and
-expansion cards.
-
-It is possible to power the board from the USB input and then connect
-the DC power supply. The board will switch over automatically to the DC
-input.
-
-.. _power-button-1:
-
-Power Button
-*********************************************
-
-A power button is connected to the input of the *TPS65941213 and TPS65941111*. This is a
-momentary switch, the same type of switch used for reset and boot
-selection on the board.
-
-If you push the button the *TPS65941213 and TPS65941111* will send an interrupt to the
-processor. It is up to the processor to then pull the **PMIC_POWER_EN**
-pin low at the correct time to power down the board. At this point, the
-PMIC is still active, assuming that the power input was not removed.
-Pressing the power button will cause the board to power up again if the
-processor puts the board in the power off mode.
-
-In power off mode, the RTC rail is still active, keeping the RTC powered
-and running off the main power input. If you remove that power, then the
-RTC will not be powered. You also have the option of using the battery
-holes on the board to connect a battery if desired as discussed in the
-next section.
-
-If you push and hold the button for greater than 8 seconds, the PMIC
-will power down. But you must release the button when the power LED
-turns off. Holding the button past that point will cause the board to
-power cycle.
-
-.. _section-6-1-7,Section 6.1.7 Power Consumption:
-
-Power Consumption
-*********************************************
-
-The power consumption of the board varies based on power scenarios and
-the board boot processes. Measurements were taken with the board in the
-following configuration:
-
-* DC powered and USB powered
-* monitor connected
-* USB HUB
-* 4GB USB flash drive
-* Ethernet connected @ 100M
-* Serial debug cable connected
-
-:ref:`table-4` is an analysis of the power consumption of the board in these various scenarios.
-
-.. _table-4,Table 4:
-
-.. list-table:: BeagleBone AI-64 Features and Specification
- :header-rows: 1
-
- * - MODE
- - USB
- - DC
- - C+USB
- * - Reset
- - TBD
- - TBD
- - TBD
- * - Idling @ UBoot
- - 210
- - 210
- - 210
- * - Kernel Booting (Peak)
- - 460
- - 460
- - 460
- * - Kernel Idling
- - 350
- - 350
- - 350
- * - Kernel Idling Display Blank
- - 280
- - 280
- - 280
- * - Loading a Webpage
- - 430
- - 430
- - 430
-
-The current will fluctuate as various activates occur, such as the LEDs
-on and microSD/eMMC accesses.
-
-.. _processor-interfaces:
-
-Processor Interfaces
-*********************************************
-
-The processor interacts with the *TPS65941213 and TPS65941111* via several different
-signals. Each of these signals is described below.
-
-.. _bbai64-i2c0:
-
-I2C0
-************
-
-I2C0 is the control interface between the processor and the *TPS65941213 and TPS65941111*.
-It allows the processor to control the registers inside the *TPS65941213 and TPS65941111*
-for such things as voltage scaling and switching of the input rails.
-
-.. _pmc_powr_en:
-
-PMIC_POWR_EN
-******************
-
-On power up the *VDD_RTC* rail activates first. After the RTC circuitry
-in the processor has activated it instructs the *TPS65941213 and TPS65941111* to initiate
-a full power up cycle by activating the *PMIC_POWR_EN* signal by taking
-it HI. When powering down, the processor can take this pin low to start
-the power down process.
-
-.. _ldo_good:
-
-LDO_GOOD
-*********************
-
-This signal connects to the *RTC_PORZn* signal, RTC power on reset. The
-small “*n*†indicates that the signal is an active low signal. Word
-processors seem to be unable to put a bar over a word so the**n** is
-commonly used in electronics. As the RTC circuitry comes up first, this
-signal indicates that the LDOs, the 1.8V VRTC rail, is up and stable.
-This starts the power up process.
-
-.. _pmic_pgood:
-
-PMIC_PGOOD
-******************
-
-Once all the rails are up, the *PMIC_PGOOD* signal goes high. This
-releases the**PORZn** signal on the processor which was holding the
-processor reset.
-
-.. _wakeup:
-
-WAKEUP
-**************
-
-The WAKEUP signal from the *TPS65941213 and TPS65941111* is connected to the **EXT_WAKEUP**
-signal on the processor. This is used to wake up the processor when it
-is in a sleep mode. When an event is detected by the *TPS65941213 and TPS65941111*, such
-as the power button being pressed, it generates this signal.
-
-.. _pmic_int:
-
-PMIC_INT
-************
-
-The *PMIC_INT* signal is an interrupt signal to the processor. Pressing
-the power button will send an interrupt to the processor allowing it to
-implement a power down mode in an orderly fashion, go into sleep mode,
-or cause it to wake up from a sleep mode. All of these require SW
-support.
-
-.. _power-rails:
-
-Power Rails
-***********************
-
-:ref:`figure-25` shows the connections of each of the rails from the **TPS65941213 and TPS65941111**.
-
-.. _figure-25,Figure 25:
-
-.. figure:: media/image39.jpg
- :width: 400px
- :align: center
- :caption: Power Rails
-
-VRTC Rail
-************
-
-The *VRTC* rail is a 1.8V rail that is the first rail to come up in the
-power sequencing. It provides power to the RTC domain on the processor
-and the I/O rail of the **TPS65941213 and TPS65941111**. It can deliver up to 250mA
-maximum.
-
-VDD_3V3A Rail
-*************************
-
-The *VDD_3V3A* rail is supplied by the **TPS65941213 and TPS65941111** and provides the
-3.3V for the processor rails and can provide up to 400mA.
-
-VDD_3V3B Rail
-**********************
-
-The current supplied by the *VDD_3V3A* rail is not sufficient to power
-all of the 3.3V rails on the board. So a second LDO is supplied, U4,
-a **TL5209A**, which sources the *VDD_3V3B* rail. It is powered up just
-after the *VDD_3V3A* rail.
-
-VDD_1V8 Rail
-*********************************************
-
-The *VDD_1V8* rail can deliver up to 400mA and provides the power
-required for the 1.8V rails on the processor and the display framer. This
-rail is not accessible for use anywhere else on the board.
-
-VDD_CORE Rail
-*********************************************
-
-The *VDD_CORE* rail can deliver up to 1.2A at 1.1V. This rail is not
-accessible for use anywhere else on the board and connects only to the
-processor. This rail is fixed at 1.1V and should not be adjusted by SW
-using the PMIC. If you do, then the processor will no longer work.
-
-VDD_MPU Rail
-*********************************************
-
-The *VDD_MPU* rail can deliver up to 1.2A. This rail is not accessible
-for use anywhere else on the board and connects only to the processor.
-This rail defaults to 1.1V and can be scaled up to allow for higher
-frequency operation. Changing of the voltage is set via the I2C
-interface from the processor.
-
-VDDS_DDR Rail
-*********************************************
-
-The *VDDS_DDR* rail defaults to**1.5V** to support the LPDDR4 rails and
-can deliver up to 1.2A. It is possible to adjust this voltage rail down
-to *1.35V* for lower power operation of the LPDDR4 device. Only LPDDR4
-devices can support this voltage setting of 1.35V.
-
-Power Sequencing
-*********************************************
-
-The power up process is consists of several stages and events. :ref:`figure-26`
-describes the events that make up the power up process for the
-processer from the PMIC. This diagram is used elsewhere to convey
-additional information. I saw no need to bust it up into smaller
-diagrams. It is from the processor datasheet supplied by Texas
-Instruments.
-
-.. _figure-26,Figure 26:
-
-.. figure:: media/image40.*
- :width: 400px
- :align: center
- :caption: Power Rail Power Up Sequencing
-
-:ref:`figure-27` the voltage rail sequencing for the**TPS65941213 and TPS65941111** as it
-powers up and the voltages on each rail. The power sequencing starts at
-15 and then goes to one. That is the way the *TPS65941213 and TPS65941111* is configured.
-You can refer to the TPS65941213 and TPS65941111 datasheet for more information.
-
-.. _figure-27,Figure 27:
-
-.. figure:: media/image41.*
- :width: 400px
- :align: center
- :caption: TPS65941213 and TPS65941111 Power Sequencing Timing
-
-.. _power-led:
-
-Power LED
-*********************************************
-
-The power LED is a blue LED that will turn on once the *TPS65941213 and TPS65941111* has
-finished the power up procedure. If you ever see the LED flash once,
-that means that the**TPS65941213 and TPS65941111** started the process and encountered an
-issue that caused it to shut down. The connection of the LED is shown in
-:ref:`figure-25`.
-
-.. _TPS65941213-and-TPS65941111-power-up-process:
-
-TPS65941213 and TPS65941111 Power Up Process
-*********************************************
-
-:ref:`figure-28` shows the interface between the **TPS65941213 and TPS65941111** and the
-processor. It is a cut from the PDF form of the schematic and reflects
-what is on the schematic.
-
-.. _figure-28,Figure 28:
-
-.. figure:: media/image42.jpg
- :width: 400px
- :align: center
- :caption: Power Processor Interfaces
-
-When voltage is applied, DC or USB, the *TPS65941213 and TPS65941111* connects the power
-to the SYS output pin which drives the switchers and LDOs in
-the **TPS65941213 and TPS65941111**.
-
-At power up all switchers and LDOs are off except for the *VRTC LDO*
-(1.8V), which provides power to the VRTC rail and controls
-the **RTC_PORZn** input pin to the processor, which starts the power up
-process of the processor. Once the RTC rail powers up, the *RTC_PORZn*
-pin, driven by the *LDO_PGOOD* signal from the *TPS65941213 and TPS65941111*, of the
-processor is released.
-
-Once the *RTC_PORZn* reset is released, the processor starts the
-initialization process. After the RTC stabilizes, the processor launches
-the rest of the power up process by activating the**PMIC_POWER_EN**
-signal that is connected to the *TPS65941213 and TPS65941111* which starts the *TPS65941213 and TPS65941111*
-power up process.
-
-The *LDO_PGOOD* signal is provided by the**TPS65941213 and TPS65941111** to the processor.
-As this signal is 1.8V from the *TPS65941213 and TPS65941111* by virtue of the *TPS65941213 and TPS65941111*
-VIO rail being set to 1.8V, and the *RTC_PORZ* signal on the processor
-is 3.3V, a voltage level shifter, *U4*, is used. Once the LDOs and
-switchers are up on the *TPS65941213 and TPS65941111*, this signal goes active releasing
-the processor. The LDOs on the *TPS65941213 and TPS65941111* are used to power the VRTC
-rail on the processor.
-
-.. _processor-control-interface:
-
-Processor Control Interface
-*********************************************
-
-:ref:`figure-28` above shows two interfaces between the processor and
-the**TPS65941213 and TPS65941111** used for control after the power up sequence has
-completed.
-
-The first is the *I2C0* bus. This allows the processor to turn on and
-off rails and to set the voltage levels of each regulator to supports
-such things as voltage scaling.
-
-The second is the interrupt signal. This allows the *TPS65941213 and TPS65941111* to alert
-the processor when there is an event, such as when the power button is
-pressed. The interrupt is an open drain output which makes it easy to
-interface to 3.3V of the processor.
-
-.. _low-power-mode-support:
-
-Low Power Mode Support
-*********************************************
-
-This section covers three general power down modes that are available.
-These modes are only described from a Hardware perspective as it relates
-to the HW design.
-
-RTC Only
-*********************************************
-
-In this mode all rails are turned off except the *VDD_RTC*. The
-processor will need to turn off all the rails to enter this mode.
-The **VDD_RTC** staying on will keep the RTC active and provide for the
-wakeup interfaces to be active to respond to a wake up event.
-
-RTC Plus DDR
-*********************************************
-
-In this mode all rails are turned off except the *VDD_RTC* and
-the **VDDS_DDR**, which powers the LPDDR4 memory. The processor will need
-to turn off all the rails to enter this mode. The *VDD_RTC* staying on
-will keep the RTC active and provide for the wakeup interfaces to be
-active to respond to a wake up event.
-
-The *VDDS_DDR* rail to the LPDDR4 is provided by the 1.5V rail of
-the **TPS65941213 and TPS65941111** and with *VDDS_DDR* active, the LPDDR4 can be placed in
-a self refresh mode by the processor prior to power down which allows
-the memory data to be saved.
-
-Currently, this feature is not included in the standard software
-release. The plan is to include it in future releases.
-
-Voltage Scaling
-*********************************************
-
-For a mode where the lowest power is possible without going to sleep,
-this mode allows the voltage on the ARM processor to be lowered along
-with slowing the processor frequency down. The I2C0 bus is used to
-control the voltage scaling function in the *TPS65941213 and TPS65941111*.
-
-.. _sitara-am3358bzcz100-processor:
-
-TI J721E DRA829/TDA4VM/AM752x Processor
------------------------------------------
-
-The board is designed to use the TI J721E DRA829/TDA4VM/AM752x processor in the
-15 x 15 package.
-
-.. _description:
-
-Description
-*********************************************
-
-:ref:`figure-29` is a high level block diagram of the processor. For more information on the processor, go to `https://www.ti.com/product/TDA4VM <https://www.ti.com/product/TDA4VM>`_
-
-.. _figure-29,Figure 29:
-
-.. figure:: media/image43.*
- :width: 400px
- :align: center
- :caption: Jacinto TDA4VMBZCZ Block Diagram
-
-
-.. _high-level-features:
-
-High Level Features
-*********************************************
-
-:ref:`table-5` below shows a few of the high level features of the Jacinto
-processor.
-
-.. _table-5,Table 5:
-
-
-.. list-table:: Table 5: Processor Features
- :header-rows: 1
-
- * - Operating Systems
- - Linux, Android, Windows Embedded CE,QNX,ThreadX
- - MMC/SD
- - 3
- * - Standby Power
- - 7 mW
- - CAN
- - 2
- * - ARM CPU
- - 1 ARM Cortex-A8
- - UART (SCI)
- - 6
- * - ARM MHz (Max.)
- - 275,500,600,800,1000
- - ADC
- - 8-ch 12-bit
- * - ARM MIPS (Max.)
- - 1000,1200,2000
- - PWM (Ch)
- - 3
- * - Graphics Acceleration
- - 1 3D
- - eCAP
- - 3
- * - Other Hardware Acceleration
- - 2 PRU-ICSS,Crypto Accelerator
- - eQEP
- - 3
- * - On-Chip L1 Cache
- - 64 KB (ARM Cortex-A8)
- - RTC
- - 1
- * - On-Chip L2 Cache
- - 256 KB (ARM Cortex-A8)
- - I2C
- - 3
- * - Other On-Chip Memory
- - 128 KB
- - McASP
- - 2
- * - Display Options
- - LCD
- - SPI
- - 2
- * - General Purpose Memory
- - 1 16-bit (GPMC, NAND flash, NOR Flash, SRAM)
- - DMA (Ch)
- - 64-Ch EDMA
- * - DRAM
- - 1 16-bit (LPDDR-400,DDR2-532, DDR3-400)
- - IO Supply (V)
- - 1.8V(ADC),3.3V
- * - USB Ports
- - 2
- - Operating Temperature Range (C)
- - -40 to 90
-
-.. _documentation:
-
-Documentation
-**********************
-
-Full documentation for the processor can be found on the TI website at `https://www.ti.com/product/TDA4VM <https://www.ti.com/product/TDA4VM>`_ for the current processor used on the board. Make sure that you always use the latest datasheets and Technical Reference Manuals (TRM).
-
-.. _crystal-circuitry:
-
-Crystal Circuitry
-***********************
-
-:ref:`figure-30` is the crystal circuitry for the TDA4VM processor.
-
-.. _figure-30,Figure 30:
-
-.. figure:: media/image44.*
- :width: 400px
- :align: center
- :caption: Processor Crystals
-
-.. _reset-circuitry:
-
-Reset Circuitry
-*********************************************
-
-:ref:`figure-31` is the board reset circuitry. The initial power on reset is
-generated by the **TPS65941213 and TPS65941111** power management IC. It also handles the
-reset for the Real Time Clock.
-
-The board reset is the SYS_RESETn signal. This is connected to the
-NRESET_INOUT pin of the processor. This pin can act as an input or an
-output. When the reset button is pressed, it sends a warm reset to the
-processor and to the system.
-
-On the revision A5D board, a change was made. On power up, the
-NRESET_INOUT signal can act as an output. In this instance it can cause
-the SYS_RESETn line to go high prematurely. In order to prevent this,
-the PORZn signal from the TPS65941213 and TPS65941111 is connected to the SYS_RESETn line
-using an open drain buffer. These ensure that the line does not
-momentarily go high on power up.
-
-.. _figure-31,Figure 31:
-
-.. figure:: media/image45.png
- :width: 400px
- :align: center
- :caption: Board Reset Circuitry
-
-This change is also in all revisions after A5D.
-
-LPDDR4 Memory
-
-BeagleBone AI-64 uses a single MT41K256M16HA-125 512MB LPDDR4 device
-from Micron that interfaces to the processor over 16 data lines, 16
-address lines, and 14 control lines. On rev C we added the Kingston
-*KE4CN2H5A-A58* device as a source for the LPDDR4 device.
-
-The following sections provide more details on the design.
-
-.. _memory-device:
-
-Memory Device
-*********************************************
-
-The design supports the standard DDR3 and LPDDR4 x16 devices and is built
-using the LPDDR4. A single x16 device is used on the board and there is
-no support for two x8 devices. The DDR3 devices work at 1.5V and the
-LPDDR4 devices can work down to 1.35V to achieve lower power. The LPDDR4 comes in a 96-BALL FBGA package
-with 0.8 mil pitch. Other standard DDR3 devices can also be supported,
-but the LPDDR4 is the lower power device and was chosen for its ability
-to work at 1.5V or 1.35V. The standard frequency that the LPDDR4 is run
-at on the board is 400MHZ.
-
-.. _ddr3l-memory-design:
-
-LPDDR4 Memory Design
-*********************************************
-
-:ref:`figure-32` is the schematic for the LPDDR4 memory device. Each of the
-groups of signals is described in the following lines.
-
-*Address Lines:* Provide the row address for ACTIVATE commands, and the
-column address and auto pre-charge bit (A10) for READ/WRITE commands, to
-select one location out of the memory array in the respective bank. A10
-sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address
-inputs also provide the op-code during a LOAD MODE command. Address
-inputs are referenced to VREFCA. A12/BC#: When enabled in the mode
-register (MR), A12 is sampled during READ and WRITE commands to
-determine whether burst chop (on-the-fly) will be performed (HIGH BL8
-or no burst chop, LOW BC4 burst chop).
-
-*Bank Address Lines:* BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA.
-
-*CK and CK# Lines:* are differential clock inputs. All address and
-control input signals are sampled on the crossing of the positive edge
-of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is
-referenced to the crossings of CK and CK#.
-
-*Clock Enable Line:* CKE enables (registered HIGH) and disables
-(registered LOW) internal circuitry and clocks on the DRAM. The specific
-circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM
-configuration and operating mode. Taking CKE LOW provides PRECHARGE
-power-down and SELF REFRESH operations (all banks idle) or active
-power-down (row active in any bank). CKE is synchronous for powerdown
-entry and exit and for self refresh entry. CKE is asynchronous for self
-refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT)
-are disabled during powerdown. Input buffers (excluding CKE and RESET#)
-are disabled during SELF REFRESH. CKE is referenced to VREFCA.
-
-.. _figure-32,Figure 32:
-
-.. figure:: media/image46.*
- :width: 400px
- :align: center
- :caption: LPDDR4 Memory Design
-
-*Chip Select Line:* CS# enables (registered LOW) and disables
-(registered HIGH) the command decoder. All commands are masked when CS#
-is registered HIGH. CS# provides for external rank selection on systems
-with multiple ranks. CS# is considered part of the command code. CS# is
-referenced to VREFCA.
-
-*Input Data Mask Line:* DM is an input mask signal for write data. Input
-data is masked when DM is sampled HIGH along with the input data during
-a write access. Although the DM ball is input-only, the DM loading is
-designed to match that of the DQ and DQS balls. DM is referenced to
-VREFDQ.
-
-*On-die Termination Line:* ODT enables (registered HIGH) and disables
-(registered LOW) termination resistance internal to the LPDDR4 SDRAM.
-When enabled in normal operation, ODT is only applied to each of the
-following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS,
-DQS#, and DM for the x4. The ODT input is ignored if disabled via the
-LOAD MODE command. ODT is referenced to VREFCA.
-
-.. _power-rails-1:
-
-Power Rails
-******************
-
-The *LPDDR4* memory device and the DDR3 rails on the processor are
-supplied by the**TPS65941213 and TPS65941111**. Default voltage is 1.5V but can be scaled
-down to 1.35V if desired.
-
-.. _vref:
-
-VREF
-***************
-
-The *VREF* signal is generated from a voltage divider on the **VDDS_DDR**
-rail that powers the processor DDR rail and the LPDDR4 device itself.
-*Figure 33* below shows the configuration of this signal and the
-connection to the LPDDR4 memory device and the processor.
-
-.. _figure-33,Figure 33:
-
-.. figure:: media/image47.*
- :width: 400px
- :align: center
- :caption: LPDDR4 VREF Design
-
-
-.. _gb-emmc-memory:
-
-4GB eMMC Memory
------------------------------------
-
-The eMMC is a communication and mass data storage device that includes a
-Multi-MediaCard (MMC) interface, a NAND Flash component, and a
-controller on an advanced 11-signal bus, which is compliant with the MMC
-system specification. The nonvolatile eMMC draws no power to maintain
-stored data, delivers high performance across a wide range of operating
-temperatures, and resists shock and vibration disruption.
-
-One of the issues faced with SD cards is that across the different
-brands and even within the same brand, performance can vary. Cards use
-different controllers and different memories, all of which can have bad
-locations that the controller handles. But the controllers may be
-optimized for reads or writes. You never know what you will be getting.
-This can lead to varying rates of performance. The eMMC card is a known
-controller and when coupled with the 8bit mode, 8 bits of data instead
-of 4, you get double the performance which should result in quicker boot
-times.
-
-The following sections describe the design and device that is used on
-the board to implement this interface.
-
-.. _emmc-device:
-
-eMMC Device
-*********************************************
-
-The device used is one of two different devices:
-
-* Micron *MTFC4GLDEA 0M WT*
-* Kingston *KE4CN2H5A-A58*
-
-The package is a 153 ball WFBGA device on both devices.
-
-.. _emmc-circuit-design:
-
-eMMC Circuit Design
-*********************************************
-
-:ref:`figure-34` is the design of the eMMC circuitry. The eMMC device is
-connected to the MMC1 port on the processor. MMC0 is still used for the
-microSD card as is currently done on the BeagleBone Black. The size
-of the eMMC supplied is now 4GB.
-
-The device runs at 3.3V both internally and the external I/O rails. The
-VCCI is an internal voltage rail to the device. The manufacturer
-recommends that a 1uF capacitor be attached to this rail, but a 2.2uF
-was chosen to provide a little margin.
-
-Pullup resistors are used to increase the rise time on the signals to
-compensate for any capacitance on the board.
-
-.. _figure-34,Figure 34:
-
-.. figure:: media/image48.*
- :width: 400px
- :align: center
- :caption: eMMC Memory Design
-
-
-The pins used by the eMMC1 in the boot mode are listed below in *Table 6*.
-
-.. _table-6,Table 6:
-
-.. figure:: media/image49.*
- :width: 400px
- :align: center
- :caption: eMMC Boot Pins
-
-For eMMC devices the ROM will only support raw mode. The ROM Code reads
-out raw sectors from image or the booting file within the file system
-and boots from it. In raw mode the booting image can be located at one
-of the four consecutive locations in the main area: offset 0x0 / 0x20000
-(128 KB) / 0x40000 (256 KB) / 0x60000 (384 KB). For this reason, a
-booting image shall not exceed 128KB in size. However it is possible to
-flash a device with an image greater than 128KB starting at one of the
-aforementioned locations. Therefore the ROM Code does not check the
-image size. The only drawback is that the image will cross the
-subsequent image boundary. The raw mode is detected by reading sectors
-#0, #256, #512, #768. The content of these sectors is then verified for
-presence of a TOC structure. In the case of a *GP Device*, a
-Configuration Header (CH)*must* be located in the first sector followed
-by a *GP header*. The CH might be void (only containing a CHSETTINGS
-item for which the Valid field is zero).
-
-The ROM only supports the 4-bit mode. After the initial boot, the switch
-can be made to 8-bit mode for increasing the overall performance of the
-eMMC interface.
-
-.. _board-id-eeprom:
-
-Board ID EEPROM
------------------------------------
-
-BeagleBone is equipped with a single 32Kbit(4KB) 24LC32AT-I/OT
-EEPROM to allow the SW to identify the board. *Table 7* below defined
-the contents of the EEPROM.
-
-.. _table-7,Table 7:
-
-.. list-table:: Table 7: EEPROM Contents
- :header-rows: 1
-
- * - Name
- - Size (bytes)
- - Contents
- * - Header
- - 4
- - 0xAA, 0x55, 0x33, EE
- * - Board Name
- - 8
- - Name for board in ASCII: A335BNLT
- * - Version
- - 4
- - Hardware version code for board in ASCII: 00A3 for Rev A3, 00A4 for Rev A4, 00A5 for Rev A5,00A6 for Rev A6,00B0 for Rev B, and 00C0 for Rev C.
- * - Serial Number
- - 12
- - Serial number of the board. This is a 12 character string which is: WWYY4P16nnnn where: WW 2 digit week of the year of production YY 2 digit year of production BBBK BeagleBone AI-64 nnnn incrementing board number
- * - Configuration Option
- - 32
- - Codes to show the configuration setup on this board.All FF
- * - RSVD
- - 6
- - FF FF FF FF FF FF
- * - RSVD
- - 6
- - FF FF FF FF FF FF
- * - RSVD
- - 6
- - FF FF FF FF FF FF
- * - Available
- - 4018
- - Available space for other non-volatile codes/data
-
-:ref:`figure-35` shows the new design on the EEPROM interface.
-
-.. _figure-35,Figure 35:
-
-.. figure:: media/image50.*
- :width: 400px
- :align: center
- :caption: EEPROM Design Rev A5
-
-The EEPROM is accessed by the processor using the I2C 0 bus. The *WP*
-pin is enabled by default. By grounding the test point, the write
-protection is removed.
-
-The first 48 locations should not be written to if you choose to use the
-extras storage space in the EEPROM for other purposes. If you do, it
-could prevent the board from booting properly as the SW uses this
-information to determine how to set up the board.
-
-.. _micro-secure-digital:
-
-Micro Secure Digital
------------------------------------
-
-The microSD connector on the board will support a microSD card that can
-be used for booting or file storage on BeagleBone AI-64.
-
-.. _microsd-design:
-
-microSD Design
-*********************************************
-
-:ref:`figure-36` below is the design of the microSD interface on the board.
-
-.. _figure-36,Figure 36:
-
-.. figure:: media/image51.*
- :width: 400px
- :align: center
- :caption: microSD Design
-
-The signals *MMC0-3* are the data lines for the transfer of data between
-the processor and the microSD connector.
-
-The *MMC0_CLK* signal clocks the data in and out of the microSD card.
-
-The *MMCO_CMD* signal indicates that a command versus data is being sent.
-
-There is no separate card detect pin in the microSD specification. It
-uses *MMCO_DAT3* for that function. However, most microSD connectors
-still supply a CD function on the connectors. In BeagleBone AI-64
-design, this pin is connected to the**MMC0_SDCD** pin for use by the
-processor. You can also change the pin to *GPIO0_6*, which is able to
-wake up the processor from a sleep mode when an microSD card is inserted
-into the connector.
-
-Pullup resistors are provided on the signals to increase the rise times
-of the signals to overcome PCB capacitance.
-
-Power is provided from the *VDD_3V3B* rail and a 10uF capacitor is
-provided for filtering.
-
-.. _user-leds:
-
-User LEDs
------------------------------------
-
-There are four user LEDs on BeagleBone AI-64. These are connected to
-GPIO pins on the processor. *Figure 37* shows the interfaces for the
-user LEDs.
-
-.. _figure-37,Figure 37:
-
-.. figure:: media/image52.*
- :width: 400px
- :align: center
- :caption: User LEDs
-
-Resistors R71-R74 were changed to 4.75K on the revision A5B and later
-boards.
-
-:ref:`table-8` shows the signals used to control the four LEDs from the
-processor.
-
-.. _table-8,Table 8:
-
-.. list-table:: Table 8: User LED Control Signals/Pins
- :header-rows: 1
-
- * - LED
- - GPIO SIGNAL
- - PROC PIN
- * - USR0
- - GPIO1_21
- - V15
- * - USR1
- - GPIO1_22
- - U15
- * - USR2
- - GPIO1_23
- - T15
- * - USR3
- - GPIO1_24
- - V16
-
-
-
-A logic level of “1†will cause the LEDs to turn on.
-
-.. _boot-configuration:
-
-Boot Configuration
------------------------------------
-
-The design supports two groups of boot options on the board. The user
-can switch between these modes via the Boot button. The primary boot
-source is the onboard eMMC device. By holding the Boot button, the user
-can force the board to boot from the microSD slot. This enables the eMMC
-to be overwritten when needed or to just boot an alternate image. The
-following sections describe how the boot configuration works.
-
-In most applications, including those that use the provided demo
-distributions available from `beagleboard.org <http://beagleboard.org/>`_ the processor-external boot code is composed of two stages. After the
-primary boot code in the processor ROM passes control, a secondary stage
-(secondary program loader -- "SPL" or "MLO") takes over. The SPL stage
-initializes only the required devices to continue the boot process, and
-then control is transferred to the third stage "U-boot". Based on the
-settings of the boot pins, the ROM knows where to go and get the SPL and
-UBoot code. In the case of BeagleBone AI-64, that is either eMMC or
-microSD based on the position of the boot switch.
-
-.. _boot-configuration-design:
-
-Boot Configuration Design
-*********************************************
-
-:ref:`figure-38` shows the circuitry that is involved in the boot
-configuration process. On power up, these pins are read by the processor
-to determine the boot order. S2 is used to change the level of one bit
-from HI to LO which changes the boot order.
-
-.. _figure-38,Figure 38:
-
-.. figure:: media/image53.*
- :width: 400px
- :align: center
- :caption: Processor Boot Configuration Design
-
-It is possible to override these setting via the expansion headers. But
-be careful not to add too much load such that it could interfere with
-the operation of the display interface or LCD panels. If you choose to
-override these settings, it is strongly recommended that you gate these
-signals with the *SYS_RESETn* signal. This ensures that after coming out
-of reset these signals are removed from the expansion pins.
-
-.. _default-boot-options:
-
-Default Boot Options
------------------------------------
-
-Based on the selected option found in :ref:`figure-39` below, each of the
-boot sequences for each of the two settings is shown.
-
-.. _figure-39,Figure 39:
-
-.. figure:: media/image54.*
- :width: 400px
- :align: center
- :caption: Processor Boot Configuration
-
-The first row in :ref:`figure-39` is the default setting. On boot, the
-processor will look for the eMMC on the MMC1 port first, followed by the
-microSD slot on MMC0, USB0 and UART0. In the event there is no microSD
-card and the eMMC is empty, UART0 or USB0 could be used as the board
-source.
-
-If you have a microSD card from which you need to boot from, hold the
-boot button down. On boot, the processor will look for the SPIO0 port
-first, then microSD on the MMC0 port, followed by USB0 and UART0. In the
-event there is no microSD card and the eMMC is empty, USB0 or UART0
-could be used as the board source.
-
-.. _ethernet:
-
-10/100/1000 Ethernet
------------------------------------
-
-BeagleBone AI-64 is equipped with a 10/100/1000 Ethernet interface.
-The design is
-described in the following sections.
-
-.. _ethernet-processor-interface:
-
-Ethernet Processor Interface
-*********************************************
-
-:ref:`figure-40` shows the connections between the processor and the PHY. The
-interface is in the MII mode of operation.
-
-.. _figure-40,Figure 40:
-
-.. figure:: media/image55.*
- :width: 400px
- :align: center
- :caption: Ethernet Processor Interface
-
-
-This is the same interface as is used on BeagleBone. No changes were
-made in this design for the board.
-
-.. _ethernet-connector-interface:
-
-Ethernet Connector Interface
-*********************************************
-
-The off board side of the PHY connections are shown in *Figure 41*
-below.
-
-.. _figure-41,Figure 41:
-
-.. figure:: media/image56.*
- :width: 400px
- :align: center
- :caption: Ethernet Connector Interface
-
-This is the same interface as is used on BeagleBone. No changes were
-made in this design for the board.
-
-.. _ethernet-phy-power-reset-and-clocks:
-
-Ethernet PHY Power, Reset, and Clocks
-*********************************************
-
-:ref:`figure-42` shows the power, reset, and lock connections to
-the **LAN8710A** PHY. Each of these areas is discussed in more detail in
-the following sections.
-
-.. _figure-42,Figure 42:
-
-.. figure:: media/image57.*
- :width: 400px
- :align: center
- :caption: Ethernet PHY, Power, Reset, and Clocks
-
-
-VDD_3V3B Rail
-*****************
-
-The VDD_3V3B rail is the main power rail for the *LAN8710A*. It
-originates at the VD_3V3B regulator and is the primary rail that
-supports all of the peripherals on the board. This rail also supplies
-the VDDIO rails which set the voltage levels for all of the I/O signals
-between the processor and the **LAN8710A**.
-
-VDD_PHYA Rail
-*******************
-
-A filtered version of VDD_3V3B rail is connected to the VDD rails of the
-LAN8710 and the termination resistors on the Ethernet signals. It is
-labeled as *VDD_PHYA*. The filtering inductor helps block transients
-that may be seen on the VDD_3V3B rail.
-
-PHY_VDDCR Rail
-*********************
-
-The *PHY_VDDCR* rail originates inside the LAN8710A. Filter and bypass
-capacitors are used to filter the rail. Only circuitry inside the
-LAN8710A uses this rail.
-
-SYS_RESET
-******************
-
-The reset of the LAN8710A is controlled via the *SYS_RESETn* signal, the
-main board reset line.
-
-Clock Signals
-*********************
-
-A crystal is used to create the clock for the LAN8710A. The processor
-uses the *RMII_RXCLK* signal to provide the clocking for the data
-between the processor and the LAN8710A.
-
-.. _lan8710a-mode-pins:
-
-LAN8710A Mode Pins
-*********************
-
-There are mode pins on the LAN8710A that sets the operational mode for
-the PHY when coming out of reset. These signals are also used to
-communicate between the processor and the LAN8710A. As a result, these
-signals can be driven by the processor which can cause the PHY not to be
-initialized correctly. To ensure that this does not happen, three low
-value pull up resistors are used. *Figure 43* below shows the three mode
-pin resistors.
-
-.. _figure-43,Figure 43:
-
-.. figure:: media/image97.*
- :width: 400px
- :align: center
- :caption: Ethernet PHY Mode Pins
-
-This will set the mode to be 111, which enables all modes and enables
-auto-negotiation.
-
-.. _hdmi-interface-1:
-
-Display Port Interface
------------------------------------
-
-BeagleBone AI-64 has an onboard Display Port framer that converts the LCD
-signals and audio signals to drive a Display Port monitor. The design uses the on chip
-internal Display Port Framer.
-
-The following sections provide more detail into the design of this
-interface.
-
-.. _supported-resolutions:
-
-Supported Resolutions
-****************************
-
-The maximum resolution supported by BeagleBone AI-64 is 1280x1024 @
-60Hz. *Table 9* below shows the supported resolutions. Not all
-resolutions may work on all monitors, but these have been tested and
-shown to work on at least one monitor. EDID is supported on the
-BeagleBone AI-64. Based on the EDID reading from the connected monitor,
-the highest compatible resolution is selected.
-
-.Table 9. HDMI Supported Monitor Adapter Resolutions
-[cols"4,1",options"header",]
-
-.. list-table:: Table 9. HDMI Supported Monitor Adapter Resolutions
- :header-rows: 1
-
- * - RESOLUTION
- - AUDIO
- * - 800 x 600 @60Hz
- -
- * - 800 x 600 @56Hz
- -
- * - 640 x 480 @75Hz
- -
- * - 640 x 480 @60Hz
- - YES
- * - 720 x 400 @70Hz
- -
- * - 1280 x 1024 @75Hz
- -
- * - 1024 x 768 @75Hz
- -
- * - 1024 x 768 @70Hz
- -
- * - 1024 x 768 @60Hz
- -
- * - 800 x 600 @75Hz
- -
- * - 800 x 600 @72Hz
- -
- * - 720 x 480 @60Hz
- - YES
- * - 1280 x 720 @60Hz
- - YES
- * - 1920x1080 @24Hz
- - YES
-
-
-.. note ::
-
- The updated software image used on the Rev A5B and later boards added support for 1920x1080@24HZ.
-
-
-Audio is limited to CEA supported resolutions. LCD panels only activate
-the audio in CEA modes. This is a function of the specification and is
-not something that can be fixed on the board via a hardware change or a
-software change.
-
-.. _hdmi-framer:
-
-Display Port Framer
-*********************************************
-
-insert processor Display Port framer doc here
-
-.. _hdmi-video-processor-interface:
-
-Display Port Video Processor Interface
-*********************************************
-
-insert processor Display Port V-interface doc here
-
-.. _hdmi-control-processor-interface:
-
-Display Port Control Processor Interface
-*********************************************
-
-insert processor Display Port C-interface doc here
-
-.. _interrupt-signal:
-
-Interrupt Signal
-*********************************************
-
-insert processor Display Port interrupt doc here
-
-.. _audio-interface:
-
-Audio Interface
-*********************************************
-
-insert processor Display Port audio doc here
-
-.. _power-connections:
-
-Power Connections
-*********************************************
-
-guesing this doesn’t exist on this device
-
-.. _hdmi-connector-interface:
-
-miniDP Connector Interface
-*********************************************
-
-insert processor Mini Display Port connector doc here
-
-.. _usb-host:
-
-USB Host
------------------------------------
-
-The board is equipped with a single USB host interface accessible from a
-single USB Type A female connector. :ref:`figure-48` is the design of the USB
-Host circuitry.
-
-.. _figure-48,Figure 48:
-
-.. figure:: media/image66.*
- :width: 400px
- :align: center
- :caption: USB Host circuit
-
-.. _power-switch:
-
-Power Switch
-*********************************************
-
-*U8* is a switch that allows the power to the connector to be turned on
-or off by the processor. It also has an over current detection that can
-alert the processor if the current gets too high via the**USB1_OC**
-signal. The power is controlled by the *USB1_DRVBUS* signal from the
-processor.
-
-.. _esd-protection:
-
-ESD Protection
-*********************************************
-
-*U9* is the ESD protection for the signals that go to the connector.
-
-.. _filter-options:
-
-Filter Options
-*********************************************
-
-*FB7* and *FB8* were added to assist in passing the FCC emissions test.
-The *USB1_VBUS* signal is used by the processor to detect that the 5V is
-present on the connector. *FB7* is populated and *FB8* is replaced with
-a .1 ohm resistor.
-
-.. _pru-icss:
-
-PRU-ICSS
------------------------------------
-
-The PRU-ICSS module is located inside the TDA4VM processor. Access to
-these pins is provided by the expansion headers and is multiplexed with
-other functions on the board. Access is not provided to all of the
-available pins.
-
-All documentation is located at http://git.beagleboard.org/beagleboard/am335x_pru_package
-
-This feature is not supported by Texas Instruments.
-
-.. _pru-icss-features:
-
-PRU-ICSS Features
-*********************************************
-
-The features of the PRU-ICSS include:
-
-Two independent programmable real-time (PRU) cores:
-
-* 32-Bit Load/Store RISC architecture
-* 8K Byte instruction RAM (2K instructions) per core
-* 8K Bytes data RAM per core
-* 12K Bytes shared RAM
-* Operating frequency of 200 MHz
-* PRU operation is little endian similar to ARM processor
-* All memories within PRU-ICSS support parity
-* Includes Interrupt Controller for system event handling
-* Fast I/O interface
-
-*16 input pins and 16 output pins per PRU core. (Not all of these are
-accessible on BeagleBone AI-64).*
-
-.. _pru-icss-block-diagram:
-
-PRU-ICSS Block Diagram
-*****************************
-
-:ref:`figure-49` is a high level block diagram of the PRU-ICSS.
-
-.. _figure-49,Figure 49:
-
-.. figure:: media/image67.*
- :width: 400px
- :align: center
- :caption: PRU-ICSS Block Diagram
-
-.. _pru-icss-pin-access:
-
-PRU-ICSS Pin Access
-*********************************************
-
-Both PRU 0 and PRU1 are accessible from the expansion headers. Some may
-not be useable without first disabling functions on the board like LCD
-for example. Listed below is what ports can be accessed on each PRU.
-
-* 8 outputs or 9 inputs PRU1
-* 13 outputs or 14 inputs
-* UART0_TXD, UART0_RXD, UART0_CTS, UART0_RTS
-
-:ref:`table-11` below shows which PRU-ICSS signals can be accessed on the
-BeagleBone AI-64 and on which connector and pins they are accessible
-from. Some signals are accessible on the same pins.
-
-.. _table-11,Table 11:
-
-.. list-table:: PRU0 and PRU1 Access
- :header-rows: 1
-
- * -
- - PIN
- - PROC
- - NAME
- -
- -
- -
- * - P8
- - 11
- - R12
- - GPIO1_13
- -
- - pr1_pru0_pru_r30_15 (Output)
- -
- * -
- - 12
- - T12
- - GPIO1_12
- -
- - pr1_pru0_pru_r30_14 (Output)
- -
- * -
- - 15
- - U13
- - GPIO1_15
- -
- - pr1_pru0_pru_r31_15 (Input)
- -
- * -
- - 16
- - V13
- - GPIO1_14
- -
- - pr1_pru0_pru_r31_14 (Input)
- -
- * -
- - 20
- - V9
- - GPIO1_31
- - pr1_pru1_pru_r30_13 (Output)
- - pr1_pru1_pru_r31_13 (INPUT)
- -
- * -
- - 21
- - U9
- - GPIO1_30
- - pr1_pru1_pru_r30_12 (Output)
- - pr1_pru1_pru_r31_12 (INPUT)
- -
- * -
- - 27
- - U5
- - GPIO2_22
- - pr1_pru1_pru_r30_8 (Output)
- - pr1_pru1_pru_r31_8 (INPUT)
- -
- * -
- - 28
- - V5
- - GPIO2_24
- - pr1_pru1_pru_r30_10 (Output)
- - pr1_pru1_pru_r31_10 (INPUT)
- -
- * -
- - 29
- - R5
- - GPIO2_23
- - pr1_pru1_pru_r30_9 (Output)
- - pr1_pru1_pru_r31_9 (INPUT)
- -
- * -
- - 39
- - T3
- - GPIO2_12
- - pr1_pru1_pru_r30_6 (Output)
- - pr1_pru1_pru_r31_6 (INPUT)
- -
- * -
- - 40
- - T4
- - GPIO2_13
- - pr1_pru1_pru_r30_7 (Output)
- - pr1_pru1_pru_r31_7 (INPUT)
- -
- * -
- - 41
- - T1
- - GPIO2_10
- - pr1_pru1_pru_r30_4 (Output)
- - pr1_pru1_pru_r31_4 (INPUT)
- -
- * -
- - 42
- - T2
- - GPIO2_11
- - pr1_pru1_pru_r30_5 (Output)
- - pr1_pru1_pru_r31_5 (INPUT)
- -
- * -
- - 43
- - R3
- - GPIO2_8
- - pr1_pru1_pru_r30_2 (Output)
- - pr1_pru1_pru_r31_2 (INPUT)
- -
- * -
- - 44
- - R4
- - GPIO2_9
- - pr1_pru1_pru_r30_3 (Output)
- - pr1_pru1_pru_r31_3 (INPUT)
- -
- * -
- - 45
- - R1
- - GPIO2_6
- - pr1_pru1_pru_r30_0 (Output)
- - pr1_pru1_pru_r31_0 (INPUT)
- -
- * -
- - 46
- - R2
- - GPIO2_7
- - pr1_pru1_pru_r30_1 (Output)
- - pr1_pru1_pru_r31_1 (INPUT)
- -
- * -
- -
- -
- -
- -
- -
- -
- * - P9
- - 17
- - A16
- - I2C1_SCL
- - pr1_uart0_txd
- -
- -
- * -
- - 18
- - B16
- - I2C1_SDA
- - pr1_uart0_rxd
- -
- -
- * -
- - 19
- - D17
- - I2C2_SCL
- - pr1_uart0_rts_n
- -
- -
- * -
- - 20
- - D18
- - I2C2_SDA
- - pr1_uart0_cts_n
- -
- -
- * -
- - 21
- - B17
- - UART2_TXD
- - pr1_uart0_rts_n
- -
- -
- * -
- - 22
- - A17
- - UART2_RXD
- - pr1_uart0_cts_n
- -
- -
- * -
- - 24
- - D15
- - UART1_TXD
- - pr1_uart0_txd
- - pr1_pru0_pru_r31_16 (Input)
- -
- * -
- - 25
- - A14
- - GPIO3_21footnote:[GPIO3_21 is also the 24.576MHZ clock input to the processor to enable HDMI audio. To use this pin the oscillator must be disabled.]
- - pr1_pru0_pru_r30_5 (Output)
- - pr1_pru0_pru_r31_5 (Input)
- -
- * -
- - 26
- - D16
- - UART1_RXD
- - pr1_uart0_rxd
- - pr1_pru1_pru_r31_16
- -
- * -
- - 27
- - C13
- - GPIO3_19
- - pr1_pru0_pru_r30_7 (Output)
- - pr1_pru0_pru_r31_7 (Input)
- -
- * -
- - 28
- - C12
- - SPI1_CS0
- - eCAP2_in_PWM2_out
- - pr1_pru0_pru_r30_3 (Output)
- - pr1_pru0_pru_r31_3 (Input)
- * -
- - 29
- - B13
- - SPI1_D0
- - pr1_pru0_pru_r30_1 (Output)
- - pr1_pru0_pru_r31_1 (Input)
- -
- * -
- - 30
- - D12
- - SPI1_D1
- - pr1_pru0_pru_r30_2 (Output)
- - pr1_pru0_pru_r31_2 (Input)
- -
- * -
- - 31
- - A13
- - SPI1_SCLK
- - pr1_pru0_pru_r30_0 (Output)
- - pr1_pru0_pru_r31_0 (Input)
- -
-
-
diff --git a/boards/beaglebone/ai-64/ch08.rst b/boards/beaglebone/ai-64/ch08.rst
deleted file mode 100644
index 47f80dd1..00000000
--- a/boards/beaglebone/ai-64/ch08.rst
+++ /dev/null
@@ -1,1835 +0,0 @@
-:orphan:
-
-.. _bbai64-cape-board-support-1:
-
-Cape Board Support
-#######################
-
-*BeagleBone AI-64* has the ability to accept up to
-four EEPROM addressable expansion boards or capes stacked onto
-the expansion headers. The word cape comes from the shape of the
-expansion board for BeagleBone boards as it is fitted around the
-Ethernet connector on the main board. For BeagleBone this notch acts as a
-key to ensure proper orientation of the cape. On AI-64 you can see a clear
-silkscreen marking for the cape orientation. Most of BeagleBone capes
-can be used with your BeagleBone AI-64 also like shown in :ref:`bbai64-cape-placement-figure` below.
-
-.. _bbai64-cape-placement-figure:
-
-.. figure:: media/ch08/cape-placement.*
- :width: 400px
- :align: center
- :caption: BeagleBone AI-64 cape placement
-
-This section describes the rules & guidelines for creating capes to ensure proper
-operation with BeagleBone AI-64 and proper interoperability with
-other capes that are intended to coexist with each other. Co-existence
-is not a requirement and is in itself, something that is impossible to
-control or administer. But, people will be able to create capes that
-operate with other capes that are already available based on public
-information as it pertains to what pins and features each cape uses.
-This information will be able to be read from the EEPROM on each cape.
-
-For those wanting to create their own capes this should not put limits on the creation of
-capes and what they can do, but may set a few basic rules that will allow
-the software to administer their operation with BeagleBone AI-64. For this
-reason there is a lot of flexibility in the specification that we hope
-most people will find it liberating in the spirit of Open Source
-Hardware. On the other hand we are sure that there are others who would like to see tighter
-control, more details, more rules and much more order to the way capes
-are handled.
-
-Over time, this specification will change and be updated, so please
-refer to the `latest version of this manual <https://git.beagleboard.org/beagleboard/beaglebone-ai-64/>`_
-prior to designing your own capes to get the latest information.
-
-.. warning::
-
- Do not apply voltage to any I/O pin when power is not supplied to the board.
- It will damage the processor and void the warranty.
-
-.. _beaglebone-ai-64-cape-compatibility:
-
-BeagleBone AI-64 Cape Compatibility
--------------------------------------------
-
-The expansion headers on BeagleBone Black and BeagleBone AI-64 provides
-similar pin configuration options on P8 and P9 expansion header pins thus provide
-cape compatibility to a certain extent. Which means most BeagleBone Black capes
-will also be compatible with BeeagleBone AI-64.
-
-.. important::
-
- This section is still being worked on, please make sure you have the latest system reference manual (SRM).
-
-
-.. todo
-
- Add BeagleBone AI-64 LCD pins information.
- Add BeagleBone AI-64 eMMC pins information.
-
-
-.. _eeprom:
-
-EEPROM
--------------------------------------------
-
-Each cape must have its own EEPROM containing information that will
-allow the software to identify the board and to configure the expansion
-headers pins during boot as needed. The one exception is proto boards intended for
-prototyping. They may or may not have an EEPROM on them. An EEPROM is
-required for all capes sold in order for them operate correctly when
-plugged into BeagleBone AI-64.
-
-The address of the EEPROM will be set via either jumpers or a dipswitch
-on each expansion board. :ref:`expansion-board-eeprom-without-write-protect-figure`
-below is the design of the EEPROM circuit.
-
-.. _expansion-board-eeprom-without-write-protect-figure:
-
-.. figure:: media/ch08/eeprom.*
- :width: 400px
- :align: center
- :caption: Expansion board EEPROM without write protect
-
-The addressing of this device requires two bytes for the address which
-is not used on smaller size EEPROMs, which only require only one byte.
-Other compatible devices may be used as well. Make sure the device you
-select supports 16 bit addressing. The part package used is at the
-discretion of the cape designer.
-
-.. _eeprom-address:
-
-EEPROM Address
-***************************
-
-In order for each cape to have a unique address, a board ID scheme is
-used that sets the address to be different depending on the setting of
-the dipswitch or jumpers on the capes. A two position dipswitch or
-jumpers is used to set the address pins of the EEPROM.
-
-It is the responsibility of the user to set the proper address for each
-board and the position in the stack that the board occupies has nothing
-to do with which board gets first choice on the usage of the expansion
-bus signals. The process for making that determination and resolving
-conflicts is left up to the SW and, as of this moment in time, this
-method is a something of a mystery due to the new Device Tree
-methodology introduced in the 3.8 kernel.
-
-Address line A2 is always tied high. This sets the allowable address
-range for the expansion cards to *0x54* to**0x57**. All other I2C
-addresses can be used by the user in the design of their capes. But,
-these addresses must not be used other than for the board EEPROM
-information. This also allows for the inclusion of EEPROM devices on the
-cape if needed without interfering with this EEPROM. It requires that A2
-be grounded on the EEPROM not used for cape identification.
-
-.. _i2c-bus:
-
-I2C Bus
-***************************
-
-The EEPROMs on each expansion board are connected to I2C2 on connector
-P9 pins 19 and 20. For this reason I2C2 must always be left connected
-and should not be changed by SW to remove it from the expansion header
-pin mux settings. If this is done, the system will be unable to detect
-the capes.
-
-The I2C signals require pullup resistors. Each board must have a 5.6K
-resistor on these signals. With four capes installed this will result in
-an effective resistance of 1.4K if all capes were installed and all the
-resistors used were exactly 5.6K. As more capes are added the resistance
-is reduced to overcome capacitance added to the signals. When no capes
-are installed the internal pullup resistors must be activated inside the
-processor to prevent I2C timeouts on the I2C bus.
-
-The I2C2 bus may also be used by capes for other functions such as I/O
-expansion or other I2C compatible devices that do not share the same
-address as the cape EEPROM.
-
-.. _eeprom-write-protect:
-
-EEPROM Write Protect
-***************************
-
-The design in :ref:`expansion-board-eeprom-with-write-protect-figure`
-has the write protect disabled. If the write
-protect is not enabled, this does expose the EEPROM to being corrupted
-if the I2C2 bus is used on the cape and the wrong address written to. It
-is recommended that a write protection function be implemented and a
-Test Point be added that when grounded, will allow the EEPROM to be
-written to. To enable write operation, Pin 7 of the EEPROM must be tied
-to ground.
-
-When not grounded, the pin is HI via pullup resistor R210 and therefore
-write protected. Whether or not Write Protect is provided is at the
-discretion of the cape designer.
-
-*Variable & MAC Memory*
-
-VSYS_IO_3V3
-
-.. _expansion-board-eeprom-with-write-protect-figure:
-
-.. figure:: media/ch08/eeprom-write-protect.*
- :width: 400px
- :align: center
- :caption: Expansion board EEPROM with write protect
-
-.. _eeprom-data-format:
-
-EEPROM Data Format
-===================
-
-:ref:`expansion-board-eeprom-table`
-shows the format of the contents of the expansion board
-EEPROM. Data is stored in Big Endian with the least significant value on
-the right. All addresses read as a single byte data from the EEPROM, but
-two byte addressing is used. ASCII values are intended to be easily read
-by the user when the EEPROM contents are dumped.
-
-*Clean/Update table*
-
-.. _expansion-board-eeprom-table:
-
-.. list-table:: Expansion Board EEPROM
- :header-rows: 1
-
- * - Name
- - Offset
- - Size (bytes)
- - Contents
- * - Header
- - 0
- - 4
- - 0xAA, 0x55, 0x33, 0xEE
- * - EEPROM Revision
- - 4
- - 2
- - Revision number of the overall format of this EEPROM in ASCII =A1
- * - Board Name
- - 6
- - 32
- - Name of board in ASCII so user can read it when the EEPROM is dumped. Up to developer of the board as to what they call the board..
- * - Version
- - 38
- - 4
- - Hardware version code for board in ASCII.Version format is up to the developer.i.e. 02.1…00A1....10A0
- * - Manufacturer
- - 42
- - 16
- - ASCII name of the manufacturer. Company or individual’s name.
- * - Part Number
- - 58
- - 16
- - ASCII Characters for the part number. Up to maker of the board.
- * - Number of Pins
- - 74
- - 2
- - Number of pins used by the daughter board including the power pins used. Decimal value of total pins 92 max, stored in HEX.
- * - Serial Number
- - 76
- - 12
- - Serial number of the board. This is a 12 character string which is: **WWYY&&&&nnnn** where, WW = 2 digit week of the year of production, YY = 2 digit year of production , &&&&=Assembly code to let the manufacturer document the assembly number or product. A way to quickly tell from reading the serial number what the board is. Up to the developer to determine. nnnn = incrementing board number for that week of production
- * - Pin Usage
- - 88
- - 148
- - Two bytes for each configurable pins of the 74 pins on the expansion connectors, MSB LSB Bit order: 15..14 ..... 1..0 Bit 15....Pin is used or not...0=Unused by cape 1=Used by cape Bit 14-13...Pin Direction.....1 0=Output 01=Input 11=BDIR Bits 12-7...Reserved........should be all zeros Bit 6....Slew Rate .......0=Fast 1=Slow Bit 5....Rx Enable.......0=Disabled 1=Enabled Bit 4....Pull Up/Dn Select....0=Pulldown 1=PullUp Bit 3....Pull Up/DN enabled...0=Enabled 1=Disabled Bits 2-0 ...Mux Mode Selection...Mode 0-7
- * - VDD_3V3B Current
- - 236
- - 2
- - Maximum current in milliamps. This is HEX value of the current in decimal 1500mA=0x05 0xDC 325mA=0x01 0x45
- * - VDD_5V Current
- - 238
- - 2
- - Maximum current in milliamps. This is HEX value of the current in decimal 1500mA=0x05 0xDC 325mA=0x01 0x45
- * - SYS_5V Current
- - 240
- - 2
- - Maximum current in milliamps. This is HEX value of the current in decimal 1500mA=0x05 0xDC 325mA=0x01 0x45
- * - DC Supplied
- - 242
- - 2
- - Indicates whether or not the board is supplying voltage on the VDD_5V rail and the current rating 000=No 1-0xFFFF is the current supplied storing the decimal quivalent in HEX format
- * - Available
- - 244
- - 32543
- - Available space for other non-volatile codes/data to be used as needed by the manufacturer or SW driver. Could also store presets for use by SW.
-
-.. _pin-usage:
-
-Pin Usage
-==========
-
-:ref:`eeprom-pin-usage-table` shows the locations in the EEPROM to set the I/O pin usage for
-the cape. It contains the value to be written to the Pad Control
-Registers. Details on this can be found in section *9.2.2* of the
-*TDA4VM Technical Reference Manual*, The table is left blank as a
-convenience and can be printed out and used as a template for creating a
-custom setting for each cape. The 16 bit integers and all 16 bit fields
-are to be stored in Big Endian format.
-
-**Bit 15 PIN USAGE** is an indicator and should be a 1 if the pin is used or 0 if it is unused.
-
-**Bits 14-7 RESERVED** is not to be used and left as 0.
-
-**Bit 6 SLEW CONTROL** 0=Fast 1=Slow
-
-**Bit 5 RX Enabled** 0=Disabled 1=Enabled
-
-**Bit 4 PU/PD** 0=Pulldown 1=Pullup.
-
-**Bit 3 PULLUP/DN** 0=Pullup/pulldown enabled 1= Pullup/pulldown disabled
-
-**Bit 2-0 MUX MODE SELECT** Mode 0-7. (refer to TRM)
-
-Refer to the TRM for proper settings of the pin MUX mode based on the
-signal selection to be used.
-
-The *AIN0-6* pins do not have a pin mux setting, but they need to be set
-to indicate if each of the pins is used on the cape. Only bit 15 is used
-for the AIN signals.
-
-
-
-.. _eeprom-pin-usage-table:
-
-.. list-table:: EEPROM Pin Usage
- :header-rows: 1
-
-
- * - `+`
- - `+`
- - `+`
- - **15**
- - **14**
- - **13**
- - **12**
- - **11**
- - **10**
- - **9**
- - **8**
- - **7**
- - **6**
- - **5**
- * - **Off set**
- - **Conn**
- - **Name**
- - **Pin Usage**
- - **Type**
- - `+`
- - **Reserved**
- - `+`
- - `+`
- - **S L E W**
- - **R X**
- - **P U - P D**
- - **P U / D E N**
- - **Mux Mode**
- * - **88**
- - **P9-22**
- - **UART2_RXD**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **90**
- - **P9-21**
- - **UART2_TXD**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **92**
- - **P9-18**
- - **I2C1_SDA**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **94**
- - **P9-17**
- - **I2C1_SCL**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **96**
- - **P9-42**
- - **GPIO0_7**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **98**
- - **P8-35**
- - **UART4_CTSN**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **100**
- - **P8-33**
- - **UART4_RTSN**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **102**
- - **P8-31**
- - **UART5_CTSN**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **104**
- - **P8-32**
- - **UART5_RTSN**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **106**
- - **P9-19**
- - **I2C2_SCL**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **108**
- - **P9-20**
- - **I2C2_SDA**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **110**
- - **P9-26**
- - **UAR*T1_RXD**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **112**
- - **P9-24**
- - **UART1_TXD**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **114**
- - **P9-41**
- - **CLKOUT2**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **116**
- - **P8-19**
- - **EHRPWM2A**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **118**
- - **P8-13**
- - **EHRPWM2B**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **120**
- - **P8-14**
- - **GPIO0_26**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **122**
- - **P8-17**
- - **GPIO0_27**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **124**
- - **P9-11**
- - **UART4_RXD**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **126**
- - **P9-13**
- - **UART4_TXD**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **128**
- - **P8-25**
- - **GPIO1_0**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **130**
- - **P8-24**
- - **GPIO1_1**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **132**
- - **P8-5**
- - **GPIO1_2**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **134**
- - **P8-6**
- - **GPIO1_3**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **136**
- - **P8-23**
- - **GPIO1_4**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **138**
- - **P8-22**
- - **GPIO1_5**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **140**
- - **P8-3**
- - **GPIO1_6**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **142**
- - **P8-4**
- - **GPIO1_7**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **144**
- - **P8-12**
- - **GPIO1_12**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **146**
- - **P8-11**
- - **GPIO1_13**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **148**
- - **P8-16**
- - **GPIO1_14**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **150**
- - **P8-15**
- - **GPIO1_15**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - **152**
- - **P9-15**
- - **GPIO1_16**
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
-
-
-.. list-table::
- :header-rows: 1
-
- * -
- -
- -
- - 15
- - 14
- - 13
- - 12
- - 11
- - 10
- - 9
- - 8
- - 7
- - 6
- - 5
- * - Off set
- - Conn
- - Name
- - Pin Usage
- - Type
- - `+`
- - Reserve
- - `+`
- - `+`
- - S L E W
- - R X
- - P U - P D
- - P U / DE N
- - Mux Mode
- * - 154
- - P9-23
- - GPIO1_17
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- * - 156
- - P9-14
- - EHRPWM1A
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- * - 158
- - P9-16
- - EHRPWM1B
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- * - 160
- - P9-12
- - GPIO1_28
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- * - 162
- - P8-26
- - GPIO1_29
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- * - 164
- - P8-21
- - GPIO1_30
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- * - 166
- - P8-20
- - GPIO1_31
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- * - 168
- - P8-18
- - GPIO2_1
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- * - 170
- - P8-7
- - TIMER4
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- -
- * - 172
- - P8-9
- - TIMER5
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 174
- - P8-10
- - TIMER6
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 176
- - P8-8
- - TIMER7
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 178
- - P8-45
- - GPIO2_6
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 180
- - P8-46
- - GPIO2_7
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 182
- - P8-43
- - GPIO2_8
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 184
- - P8-44
- - GPIO2_9
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 186
- - P8-41
- - GPIO2_10
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 188
- - P8-42
- - GPIO2_11
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 190
- - P8-39
- - GPIO2_12
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 192
- - P8-40
- - GPIO2_13
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 194
- - P8-37
- - UART5_TX`+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 196
- - P8-38
- - UART5_RX`+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 198
- - P8-36
- - UART3_CTSN
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 200
- - P8-34
- - UART3_RTSN
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 202
- - P8-27
- - GPIO2_22
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 204
- - P8-29
- - GPIO2_23
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 206
- - P8-28
- - GPIO2_24
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 208
- - P8-30
- - GPIO2_25
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 210
- - P9-29
- - SPI1_D0
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 212
- - P9-30
- - SPI1_D1
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 214
- - P9-28
- - SPI1_CS0
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 216
- - P9-27
- - GPIO3_19
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 218
- - P9-31
- - SPI1_SCLK
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 220
- - P9-25
- - GPIO3_21
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - `+`
- - `+`
- - `+`
- - 15
- - 14
- - 13
- - 12
- - 11
- - 10
- - 9
- - 8
- - 7
- - 6
- - 5
- * - Off set
- - Conn
- - Name
- - Pin Usage
- - Type
- -
- - Reserve
- -
- -
- - S L E W
- - R X
- - P U - P D
- - P U / DE N
- - Mux Mode
- * - `+`
- - `+`
- - `+`
- - `+`
- - 0
- - 0
- - 0
- - 0
- - 0
- - 0
- - 0
- - 0
- - 0
- - 0
- * - 222
- - P9-39
- - AIN0
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 224
- - P9-40
- - AIN1
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 226
- - P9-37
- - AIN2
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 228
- - P9-38
- - AIN3
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 230
- - P9-33
- - AIN4
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 232
- - P9-36
- - AIN5
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- * - 234
- - P9-35
- - AIN6
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
- - `+`
-
-
-.. _pin-usage-consideration:
-
-Pin Usage Consideration
-========================
-
-This section covers things to watch for when hooking up to certain pins
-on the expansion headers.
-
-.. _expansion-connectors-1:
-
-Expansion Connectors
-====================
-
-A combination of male and female headers is used for access to the
-expansion headers on the main board. There are three possible mounting
-configurations for the expansion headers:
-
-* **Single** -no board stacking but can be used on the top of the stack.
-* **Stacking-up** to four boards can be stacked on top of each other.
-* **Stacking with signal stealing-up** to three boards can be stacked on top of each other, but certain boards will not pass on the signals they are using to prevent signal loading or use by other cards in the stack.
-
-The following sections describe how the connectors are to be implemented
-and used for each of the different configurations.
-
-.. _non-stacking-headers-single-cape:
-
-Non-Stacking Headers-Single Cape
-=================================
-
-For non-stacking capes single configurations or where the cape can be
-the last board on the stack, the two 46 pin expansion headers use the
-same connectors. :ref:`single-expansion-connector-figure` is a picture of
-the connector. These are dual row 23 position 2.54mm x 2.54mm connectors.
-
-.. _single-expansion-connector-figure:
-
-.. figure:: media/ch08/single-expansion-connector.*
- :width: 400px
- :align: center
- :caption: Single expansion connector
-
-The connector is typically mounted on the bottom side of the board as
-shown in :ref:`single-cape-expansion-connector-figure` . These are very
-common connectors and should be easily located. You can also use two
-single row 23 pin headers for each of the dual row headers.
-
-.. _single-cape-expansion-connector-figure:
-
-.. figure:: media/ch08/proto.*
- :width: 400px
- :align: center
- :caption: Single cape expansion connector on BeagleBone Proto Cape with EEPROM from onlogic
-
-It is allowed to only populate the pins you need. As this is a
-non-stacking configuration, there is no need for all headers to be
-populated. This can also reduce the overall cost of the cape. This
-decision is up to the cape designer.
-
-For convenience listed in :ref:`single-cape-connectors-figure` are some possible
-choices for part numbers on this connector. They have varying pin lengths and
-some may be more suitable than others for your use. It should be noted, that the
-longer the pin and the further it is inserted into BeagleBone AI-64
-connector, the harder it will be to remove due to the tension on 92
-pins. This can be minimized by using shorter pins or removing those pins
-that are not used by your particular design. The first item in**Table
-18** is on the edge and may not be the best solution. Overhang is the
-amount of the pin that goes past the contact point of the connector on
-BeagleBone AI-64
-
-
-.. _single-cape-connectors-figure:
-
-.. list-table:: Single Cape Connectors
- :header-rows: 1
-
-
- * - SUPPLIER
- - PARTNUMBER
- - LENGTH(in)
- - OVERHANG(in)
- * - `Major League <http://www.mlelectronics.com/>`_
- - TSHC-123-D-03-145-G-LF
- - .145
- - .004
- * - `Major League <http://www.mlelectronics.com/>`_
- - TSHC-123-D-03-240-G-LF
- - .240
- - .099
- * - `Major League <http://www.mlelectronics.com/>`_
- - TSHC-123-D-03-255-G-LF
- - .255
- - .114
-
-
-The G in the part number is a plating option. Other options may be used
-as well as long as the contact area is gold. Other possible sources are
-Sullins and Samtec for these connectors. You will need to ensure the
-depth into the connector is sufficient
-
-.. _main-expansion-headers-stacking:
-
-Main Expansion Headers-Stacking
-================================
-
-For stacking configuration, the two 46 pin expansion headers use the
-same connectors. :ref:`expansion-connector-figure` is a picture of the
-connector. These are dual row 23 position 2.54mm x 2.54mm connectors.
-
-.. _expansion-connector-figure:
-
-.. figure:: media/ch08/expansion-connector.*
- :width: 400px
- :align: center
- :caption: Expansion Connector
-
-The connector is mounted on the top side of the board with longer tails
-to allow insertion into BeagleBone AI-64.
-:ref:`stacked-cape-expansion-connector-figure` is the
-connector configuration for the connector.
-
-.. _stacked-cape-expansion-connector-figure:
-
-.. figure:: media/ch08/can-cape.*
- :width: 250px
- :align: center
- :caption: Stacked cape expansion connector
-
-For convenience listed in *Table 18* are some possible choices for part
-numbers on this connector. They have varying pin lengths and some may be
-more suitable than others for your use. It should be noted, that the
-longer the pin and the further it is inserted into BeagleBone AI-64
-connector, the harder it will be to remove due to the tension on 92
-pins. This can be minimized by using shorter pins. There are most likely
-other suppliers out there that will work for this connector as well. If
-anyone finds other suppliers of compatible connectors that work, let us
-know and they will be added to this document. The first item in **Table
-19** is on the edge and may not be the best solution. Overhang is the
-amount of the pin that goes past the contact point of the connector on
-BeagleBone AI-64.
-
-The third part listed in :ref:`stacked-cape-connectors-figure` will have
-insertion force issues.
-
-.. _stacked-cape-connectors-figure:
-
-.. list-table:: Stacked Cape Connectors
- :header-rows: 1
-
- * - SUPPLIER
- - PARTNUMBER
- - TAIL LENGTH(in)
- - OVERHANG(in)
- * - `Major League <http://www.mlelectronics.com/>`_
- - SSHQ-123-D-06-G-LF
- - .190
- - 0.049
- * - `Major League <http://www.mlelectronics.com/>`_
- - SSHQ-123-D-08-G-LF
- - .390
- - 0.249
- * - `Major League <http://www.mlelectronics.com/>`_
- - SSHQ-123-D-10-G-LF
- - .560
- - 0.419
-
-There are also different plating options on each of the connectors
-above. Gold plating on the contacts is the minimum requirement. If you
-choose to use a different part number for plating or availability
-purposes, make sure you do not select the “LT†option.
-
-Other possible sources are Sullins and Samtec but make sure you select
-one that has the correct mating depth.
-
-.. _stacked-capes-wsignal-stealing:
-
-Stacked Capes w/Signal Stealing
-================================
-
-:ref:`stacked-with-signal-stealing-expansion-connector-figure` is the connector configuration for stackable capes that does
-not provide all of the signals upwards for use by other boards. This is
-useful if there is an expectation that other boards could interfere with
-the operation of your board by exposing those signals for expansion.
-This configuration consists of a combination of the stacking and
-nonstacking style connectors.
-
-.. _stacked-with-signal-stealing-expansion-connector-figure:
-
-.. figure:: media/ch08/stealing-expansion-connector.*
- :width: 400px
- :align: center
- :caption: Stacked with signal stealing expansion connector figure
-
-.. _retention-force:
-
-Retention Force
-================
-
-The length of the pins on the expansion header has a direct relationship
-to the amount of force that is used to remove a cape from BeagleBone
-AI-64. The longer the pins extend into the connector the harder it is to
-remove. There is no rule that says that if longer pins are used, that
-the connector pins have to extend all the way into the mating connector
-on BeagleBone AI-64, but this is controlled by the user and
-therefore is hard to control. We have also found that if you use gold
-pins, while more expensive, it makes for a smoother finish which reduces
-the friction.
-
-This section will attempt to describe the tradeoffs and things to
-consider when selecting a connector and its pin length.
-
-.. _beaglebone-ai-64-female-connectors:
-
-BeagleBone AI-64 Female Connectors
-===================================
-
-:ref:`connector-pin-insertion-depth` shows the key measurements used in calculating how much the
-pin extends past the contact point on the connector, what we call
-overhang.
-
-.. _connector-pin-insertion-depth:
-
-.. figure:: media/ch08/berg-stip-insertion.*
- :width: 400px
- :align: center
- :caption: Connector Pin Insertion Depth
-
-To calculate the amount of the pin that extends past the Point of
-Contact, use the following formula:
-
-Overhang=Total Pin Length- PCB thickness (.062) - contact point (.079)
-
-The longer the pin extends past the contact point, the more force it
-will take to insert and remove the board. Removal is a greater issue
-than the insertion.
-
-.. _signal-usage:
-
-Signal Usage
-=============
-
-Based on the pin muxing capabilities of the processor, each expansion
-pin can be configured for different functions. When in the stacking
-mode, it will be up to the user to ensure that any conflicts are
-resolved between multiple stacked cards. When stacked, the first card
-detected will be used to set the pin muxing of each pin. This will
-prevent other modes from being supported on stacked cards and may result
-in them being inoperative.
-
-In :ref:`beaglebone-ai-64-connectors` section of this document, the
-functions of the pins are defined as well as the pin muxing options.
-Refer to this section for more information on what each pin is. To
-simplify things, if you use the default name as the function for each
-pin and use those functions, it will simplify board design
-and reduce conflicts with other boards.
-
-Interoperability is up to the board suppliers and the user. This
-specification does not specify a fixed function on any pin and any pin
-can be used to the full extent of the functionality of that pin as
-enabled by the processor.
-
-*DO NOT APPLY VOLTAGE TO ANY I/O PIN WHEN POWER IS NOT SUPPLIED TO THE
-BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.*
-
-*NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES HIGH.*
-
-.. _cape-power:
-
-Cape Power
-===========
-
-This section describes the power rails for the capes and their usage.
-
-.. _main-board-power:
-
-Main Board Power
-=================
-
-The :ref:`expansion-header-voltages-table` describes the voltages from the
-main board that are available on the expansion connectors and their ratings.
-All voltages are supplied by connector**P9**. The current ratings listed are per pin.
-
-.. _expansion-header-voltages-table:
-
-
-.. list-table:: Expansion Voltages
- :header-rows: 1
-
-
- * - Current
- - Name
- - P9
- - P9
- - Name
- - Current
- * - 250mA
- - VDD_3V3B
- - 3
- - 4
- - VDD_3V3B
- - 250mA
- * - 1000mA
- - VDD_5V
- - 5
- - 6
- - VDD_5V
- - 1000mA
- * - 250mA
- - SYS_5V
- - 7
- - 8
- - SYS_5V
- - 250mA
-
-The *VSYS_IO_3V3* rail is supplied by the LDO on BeagleBone AI-64 and
-is the primary power rail for expansion boards. If the power requirement
-for the capes exceeds the current rating, then locally generated voltage
-rail can be used. It is recommended that this rail be used to power any
-buffers or level translators that may be used.
-
-*DC_VDD_5V* is the main power supply from the DC input jack. This voltage
-is not present when the board is powered via USB. The amount of current
-supplied by this rail is dependent upon the amount of current available.
-Based on the board design, this rail is limited to 1A per pin from the
-main board.
-
-The *VSYS_5V0* rail is the main rail for the regulators on the main board.
-When powered from a DC supply or USB, this rail will be 5V. The
-available current from this rail depends on the current available from
-the USB and DC external supplies.
-
-.. _expansion-board-external-power:
-
-Expansion Board External Power
-===============================
-
-A cape can have a jack or terminals to bring in whatever voltages may be
-needed by that board. Care should be taken not to let this voltage be
-fed back into any of the expansion header pins.
-
-It is possible to provide 5V to the main board from an expansion board.
-By supplying a 5V signal into the *DC_VDD_5V* rail, the main board can be
-supplied. This voltage must not exceed 5V. You should not supply any
-voltage into any other pin of the expansion connectors. Based on the
-board design, this rail is limited to 1A per pin to BeagleBone
-AI-64.
-
-*There are several precautions that need to be taken when working with
-the expansion headers to prevent damage to the board.*
-
-1. *Do not apply any voltages to any I/O pins when the board is not powered on.*
-2. *Do not drive any external signals into the I/O pins until after the VSYS_IO_3V3 rail is up.*
-3. *Do not apply any voltages that are generated from external sources.*
-4. *If voltages are generated from the DC_VDD_5V signal, those supplies must not become active until after the VSYS_IO_3V3 rail is up.*
-5. *If you are applying signals from other boards into the expansion headers, make sure you power the board up after you power up the BeagleBone AI-64 or make the connections after power is applied on both boards.*
-
-*Powering the processor via its I/O pins can cause damage to the processor.*
-
-**TODO: Add BeagleBone AI-64 cape mechanical characteristics**
-
-.. _standard-cape-size:
-
-Standard Cape Size
-===================
-
-:ref:`cape-board-dimensions-figure` shows the outline of the standard cape. The dimensions are in inches.
-
-.. _cape-board-dimensions-figure:
-
-.. figure:: media/ch08/cape-dimension.*
- :width: 400px
- :align: center
- :caption: Cape board dimensions
-
-A notch is provided for BeagleBone Ethernet connector to stick up higher than
-the cape when mounted. This also acts as a key function to ensure that
-the cape is oriented correctly. Space is also provided to allow access
-to the user LEDs and reset button on BeagleBone board. On BeagleBone AI-64 board
-align it with the notch on the board silkscreen.
-
-.. _extended-cape-size:
-
-Extended Cape Size
-===================
-
-Capes larger than the standard board size are also allowed. A good
-example would be the new BeagleBone AI-64 robotics cape.
-There is no practical limit to the sizes of these types of boards.
-The notch is also optional, but it is up to the supplier to ensure that the
-cape is not plugged incorrectly on BeagleBone AI-64 such that damage would
-be cause to BeagleBone AI-64. Any such damage will be the responsibility of the
-supplier of such a cape to repair. As with all capes, the EEPROM is required and
-compliance with the power requirements must be adhered to.
-
-
diff --git a/boards/beaglebone/ai-64/ch09.rst b/boards/beaglebone/ai-64/ch09.rst
deleted file mode 100644
index 629a1f64..00000000
--- a/boards/beaglebone/ai-64/ch09.rst
+++ /dev/null
@@ -1,41 +0,0 @@
-.. _BeagleBone-AI-64-Mechanical:
-
-BeagleBone AI-64 Mechanical
-#############################
-
-.. _dimensions-and-weight:
-
-Dimensions and Weight
-------------------------------------
-
-Size: 102.5 x 80 (4" x 3.15")
-
-Max height: #TODO#
-
-PCB Layers: #TODO#
-
-PCB thickness: 2mm (0.08")
-
-RoHS Compliant: Yes
-
-Weight: 192gm
-
-.. _silkscreen-and-component-locations:
-
-Silkscreen and Component Locations
-------------------------------------
-
-.. figure:: media/ch09/board-dimensions.*
- :width: 400px
- :align: center
- :caption: Board Dimensions
-
-.. figure:: media/ch09/top-silkscreen.*
- :width: 400px
- :align: center
- :caption: Top silkscreen
-
-.. figure:: media/ch09/bottom-silkscreen.*
- :width: 400px
- :align: center
- :caption: Bottom silkscreen
diff --git a/boards/beaglebone/ai-64/ch10.rst b/boards/beaglebone/ai-64/ch10.rst
deleted file mode 100644
index da9ddf57..00000000
--- a/boards/beaglebone/ai-64/ch10.rst
+++ /dev/null
@@ -1,40 +0,0 @@
-.. _bbai64-pictures:
-
-Pictures
-##########
-
-.. figure:: media/ch10/front.*
- :width: 400px
- :align: center
- :caption: BeagleBone AI-64 front
-
-.. figure:: media/ch10/back.*
- :width: 400px
- :align: center
- :caption: BeagleBone AI-64 back
-
-.. figure:: media/ch10/back-heatsink.*
- :width: 400px
- :align: center
- :caption: BeagleBone AI-64 back with heatsink
-
-.. figure:: media/bbai64-45-front.*
- :width: 400px
- :align: center
- :caption: BeagleBone AI-64 front at 45° angle
-
-.. figure:: media/ch10/45-back.*
- :width: 400px
- :align: center
- :caption: BeagleBone AI-64 back at 45° angle
-
-.. figure:: media/ch10/45-back-heatsink.*
- :width: 400px
- :align: center
- :caption: BeagleBone AI-64 back with heatsink at 45° angle
-
-.. figure:: media/ch10/feature.*
- :width: 400px
- :align: center
- :caption: BeagleBone AI-64 ports
-
diff --git a/boards/beaglebone/ai-64/ch11.rst b/boards/beaglebone/ai-64/ch11.rst
deleted file mode 100644
index da33b7d3..00000000
--- a/boards/beaglebone/ai-64/ch11.rst
+++ /dev/null
@@ -1,69 +0,0 @@
-.. _beaglebone-ai-64-support-information:
-
-Support Information
-####################
-
-All support for this design is through BeagleBoard.org community at: link: `BeagleBoard.org forum <https://forum.beagleboard.org/>`_ .
-
-
-.. _hardware-design:
-
-Hardware Design
-------------------
-
-You can find all BeagleBone AI-64 hardware files `here <https://git.beagleboard.org/beagleboard/beaglebone-ai-64>`_ under the `hw` folder.
-
-
-.. _software-updates:
-
-Software Updates
------------------
-
-Follow instructions below to download the latest image for your BeagleBone AI-64:
-
-1. Go to `BeagleBoard.org distro <https://www.beagleboard.org/distros>`_ page.
-2. :ref:`filter-software-distribution-AI-64` from dropdown and download the image.
-
-.. _filter-software-distribution-AI-64:
-
-.. figure:: images/ch11/distros.png
- :align: center
- :alt: Filter Software Distributions for BeagleBone AI-64
-
- Filter Software Distributions for BeagleBone AI-64
-
-.. tip::
- You can follow the :ref:`flash-latest-image` guide for more information on
- flashing the downloaded image to your board.
-
-To see what SW revision is loaded into the eMMC check `/etc/dogtag`.
-It should look something like as shown below,
-
-```
-root@BeagleBone:~# cat /etc/dogtag
-BeagleBoard.org Debian Bullseye Xfce Image 2022-01-14
-```
-
-.. _rma-support:
-
-RMA Support
--------------------------------------
-
-If you feel your board is defective or has issues, request an Return Merchandise Application (RMA) by filling out the form at http://beagleboard.org/support/rma . You will need the serial number and revision of the board. The serial numbers and revisions keep moving. Different boards can have different locations depending on when they were made. The following figures show the three locations of the serial and revision number.
-
-.. _trouble-shooting-video-output-issues:
-
-Troubleshooting video output issues
--------------------------------------
-
-.. warning::
-
- When connecting to an HDMI monitor, make sure your miniDP adapter is *active*. A *passive* adapter will not work. See :ref:`display-adapters-figure`.
-
-
-.. _getting-help:
-
-Getting Help
-*************
-
-If you need some up to date troubleshooting techniques, you can post your queries on link: `BeagleBoard.org forum <https://forum.beagleboard.org/>`_
diff --git a/boards/beaglebone/ai-64/index.rst b/boards/beaglebone/ai-64/index.rst
index 1941791c..dc2cedac 100644
--- a/boards/beaglebone/ai-64/index.rst
+++ b/boards/beaglebone/ai-64/index.rst
@@ -40,14 +40,9 @@ hardware examples and dozens of readily available embedded expansion options ava
.. toctree::
:maxdepth: 1
- ch01
- ch02
- ch03
- ch04
- ch05
- ch07
- ch09
- ch10
- ch11
- update
+ 01-introduction
+ 02-quick-start
+ 03-design-and-specifications
+ 04-connectors-and-pinouts
+ 05-demos-and-tutorials
edge_ai_apps/index
diff --git a/boards/beaglebone/ai-64/media/chapter-thumbnails/06-support-documents.jpg b/boards/beaglebone/ai-64/media/chapter-thumbnails/06-support.jpg
similarity index 100%
rename from boards/beaglebone/ai-64/media/chapter-thumbnails/06-support-documents.jpg
rename to boards/beaglebone/ai-64/media/chapter-thumbnails/06-support.jpg
diff --git a/boards/beaglebone/ai-64/update.rst b/boards/beaglebone/ai-64/update.rst
deleted file mode 100644
index 576492b5..00000000
--- a/boards/beaglebone/ai-64/update.rst
+++ /dev/null
@@ -1,60 +0,0 @@
-.. _bbai64-update:
-
-Update software on BeagleBone AI-64
-###################################
-
-Production boards currently ship with the factory-installed 2022-01-14-8GB image. To upgrade from the software image on your BeagleBone AI-64 to the latest, you don't need to completely reflash the board. If you do want to reflash it, visit the flashing instructions on the getting started page.
-Factory Image update (without reflashing)…
-
-.. code-block:: bash
- :linenos:
-
- sudo apt update
- sudo apt install --only-upgrade bb-j721e-evm-firmware generic-sys-mods
- sudo apt upgrade
-
-Update U-Boot:
-==============
-
-to ensure only tiboot3.bin is in boot0, the pre-production image we tried to do more in boot0, but failed…
-
-.. code-block:: bash
- :linenos:
-
- sudo /opt/u-boot/bb-u-boot-beagleboneai64/install-emmc.sh
- sudo /opt/u-boot/bb-u-boot-beagleboneai64/install-microsd.sh
- sudo reboot
-
-Update Kernel and SGX modules:
-==============================
-
-.. code-block:: bash
- :linenos:
-
- sudo apt install bbb.io-kernel-5.10-ti-k3-j721e
-
-Update xfce:
-============
-
-.. code-block:: bash
- :linenos:
-
- sudo apt install bbb.io-xfce4-desktop
-
-Update ti-edge-ai 8.2 examples
-==============================
-
-.. code-block:: bash
- :linenos:
-
- sudo apt install ti-edgeai-8.2-base ti-vision-apps-8.2 ti-vision-apps-eaik-firmware-8.2
-
-Cleanup:
-========
-
-.. code-block:: bash
- :linenos:
-
- sudo apt autoremove --purge
-
-
--
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