diff --git a/Documentation/devicetree/bindings/net/ti,am654-cpsw-nuss.txt b/Documentation/devicetree/bindings/net/ti,am654-cpsw-nuss.txt
index 314c9b9a2238c2abbe35e96a942759e187b1bdc4..448939cafe1ce431f5f8209fbe4abf037056f728 100644
--- a/Documentation/devicetree/bindings/net/ti,am654-cpsw-nuss.txt
+++ b/Documentation/devicetree/bindings/net/ti,am654-cpsw-nuss.txt
@@ -1,140 +1 @@
-TI AM654 SoC Gigabit Ethernet Switch (CPSW) subsystem Device Tree Bindings
-------------------------------------------------------
-
-The TI am654 SoC Gigabit Ethernet Switch subsystem (CPSW NUSS) has two ports and
-provides Ethernet packet communication for the device and can be configured
-as an Ethernet switch. CPSW NUSS features: the Reduced Gigabit Media Independent
-Interface (RGMII), Reduced Media Independent Interface (RMII), and the
-Management Data Input/Output (MDIO) interface for physical layer device
-(PHY) management.
-
-The TI am654 SoC has integrated two-port Gigabit Ethernet Switch subsystem
-into device MCU domain named MCU_CPSW0. One Ethernet port (port 1) with
-selectable RGMII and RMII interfaces and an internal Communications
-Port Programming Interface (CPPI) port (Host port 0).
-
-Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
-and on RX channels operating by TI am654 NAVSS Unified DMA Peripheral Root
-Complex (UDMA-P) controller.
-
-Required properties:
-- compatible : Should be "ti,am654-cpsw-nuss" or
- "ti,j721e-cpsw-nuss"
-- reg : physical base address and size of the CPSW NUSS registers map
-- reg-names : should be "cpsw_nuss"
-
-- clocks : CPSW NUSS functional clock
-- clock-names : should be "fck"
- See Documentation/devicetree/bindings/clock/ti,sci-clk.txt
-- power-domains : CPSW NUSS power domain
- See Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
-
-- dma-coherent : indicates that CPSW NUSS operates with coherent memory.
-- dmas : list of UDMA-P controller channels specifiers
-- dma-names : should be "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
- "tx7", "rx";
- See Documentation/devicetree/bindings/dma/ti/k3-udma.txt
-
-
-
-Required Sub-nodes:
-
-- ethernet-ports : contains CPSW NUSS ports descriptions
- Required properties - all ports:
- - reg : CPSW NUSS port number. Should be for TI am654 SoC
- 1.. - external Ethernet ports
-
- Optional properties - all ports:
- - label : Describes the label associated with this port
-
- Required properties for - external Ethernet ports:
- - phy-mode : operation mode of the PHY interface [1]
- - phy-handle : phandle, specifies a reference to a node representing
- a PHY device [1]
-
- Optional properties for - external Ethernet ports:
- - ti,mac-only: port operates in MAC only mode
- - mac-address : array of 6 bytes, specifies the MAC address. Always
- accounted first if present [1]
- - ti,syscon-efuse: tuple of two cells. First is phandle on syscon System
- Control Module (SCM) node. Second is offset inside SCM points on
- efuse registers containing Ethernet MAC address.
- Accounted second if "mac-address" doesn't present.
-
-- mdio : CPSW NUSS MDIO bus definition
- See Documentation/devicetree/bindings/net/mdio.txt
-
-- cpts : The Common Platform Time Sync (CPTS) module definition
- Documentation/devicetree/bindings/net/ti,am654-cpts.txt
-
-[1] See Documentation/devicetree/bindings/net/ethernet.txt
-
-Examples:
-
-mcu_cpsw: ethernet@046000000 {
- compatible = "ti,am654-cpsw-nuss";
- #address-cells = <2>;
- #size-cells = <2>;
- reg = <0x0 0x46000000 0x0 0x200000>;
- reg-names = "cpsw_nuss";
- ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
- dma-coherent;
- clocks = <&k3_clks 5 10>;
- clock-names = "fck";
- power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
-
- dmas = <&mcu_udmap 0xF000>,
- <&mcu_udmap 0xF001>,
- <&mcu_udmap 0xF002>,
- <&mcu_udmap 0xF003>,
- <&mcu_udmap 0xF004>,
- <&mcu_udmap 0xF005>,
- <&mcu_udmap 0xF006>,
- <&mcu_udmap 0xF007>,
- <&mcu_udmap 0x7000>;
- dma-names = "tx0", "tx1", "tx2", "tx3",
- "tx4", "tx5", "tx6", "tx7",
- "rx";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpsw_port1: port@1 {
- reg = <1>;
- ti,mac-only;
- ti,label = "port1";
- ti,syscon-efuse = <&mcu_conf 0x200>;
- phys = <&phy_gmii_sel 1>;
- };
- };
-
- davinci_mdio: mdio {
- compatible = "ti,cpsw-mdio","ti,davinci_mdio";
- reg = <0x0 0xf00 0x0 0x100>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&k3_clks 5 10>;
- clock-names = "fck";
- bus_freq = <1000000>;
- };
-
- cpts {
- clocks = <&mcu_cpsw_cpts_mux>;
- clock-names = "cpts";
- interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
-
- mcu_cpsw_cpts_mux: cpts_refclk_mux {
- #clock-cells = <0>;
- clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
- <&k3_clks 157 91>, <&k3_clks 157 77>,
- <&k3_clks 157 102>, <&k3_clks 157 80>,
- <&k3_clks 120 3>, <&k3_clks 121 3>;
- assigned-clocks = <&mcu_cpsw_cpts_mux>;
- assigned-clock-parents = <&k3_clks 118 5>;
- };
- };
-};
+This file has moved to ti,k3-am654-cpsw-nuss.yaml.
diff --git a/Documentation/devicetree/bindings/net/ti,am654-cpts.txt b/Documentation/devicetree/bindings/net/ti,am654-cpts.txt
index 96b1df2c83f89a60b4ccf5dc39d20130d875566d..e0863abb54242a95409b976db11484cfdd3dd750 100644
--- a/Documentation/devicetree/bindings/net/ti,am654-cpts.txt
+++ b/Documentation/devicetree/bindings/net/ti,am654-cpts.txt
@@ -1,110 +1 @@
-TI AM65x SoC The Common Platform Time Sync (CPTS) module Device Tree Bindings
-------------------------------------------------------
-
-The CPTS module is used to facilitate host control of time sync operations.
-Main features of CPTS module are:
-- Supports the selection of multiple external clock sources
-- Software control of time sync events via interrupt or polling
-- Supports hardware timestamp push inputs (HWx_TS_PUSH)
-- Supports timestamp counter compare output (TS_COMP)
-- Supports timestamp counter bit output (TS_SYNC)
-- Supports timestamp Generator function outputs (TS_GENFx)
-- Supports 64-bit timestamp mode in ns with ppm and nudge adjustment.
-Depending on integration it enables compliance with the IEEE 1588-2008 standard
-for a precision clock synchronization protocol, Ethernet Enhanced Scheduled
-Traffic Operations (CPTS_ESTFn) and PCIe Subsystem Precision Time
-Measurement (PTM)
-
-TI AM65x SoC has several similar Time Sync (CPTS) modules integrated into the
-different parts of the system which could be synchronized with each other:
-- Main CPTS
-- MCU CPSW CPTS with IEEE 1588-2008 support
-- PCIe subsystem CPTS for PCIe Subsystem Precision Time Measurement (PTM)
- support
-
-Properties:
-- compatible : Should be "ti,am65-cpts" or
- "ti,j721e-cpts"
-- reg : physical base address and size of the CPTS registers map
-- reg-names : should be "cpts"
- Depending on CPTS module integration and when CPTS is integral part of
- another module (MCU CPSW for example) "compatible" and "reg" can
- be omitted - parent module is fully responsible for CPTS enabling and
- configuration.
-- clocks : CPTS reference clock. Should point on cpts_refclk_mux clock.
-- clock-names : should be "cpts"
-- interrupts-extended : CPTS events interrupt specifier
-- interrupt-names : should be "cpts"
-
-Required Sub-nodes:
-- refclk-mux : CPTS reference clock multiplexer clock
- Required properties:
- - clocks : List of phandle and clock specifier pairs, one pair
- for each possible CPTS reference clock input
- - assigned-clocks : phandle on cpts_refclk_mux
- - assigned-clock-parents : phandle on selected CPTS reference clock
- Selection of CPTS reference clock expected to be done in board files.
- By default first listed clock will be selected as CPTS reference clock.
-
-Optional properties:
-- ti,cpts-periodic-outputs : Number of timestamp Generator function
- outputs (TS_GENFx)
-- ti,cpts-ext-ts-inputs : Number of hardware timestamp push inputs (HWx_TS_PUSH)
-- ti,pps : pair of HWx_TS_PUSH input and TS_GENFy output indexes used for
- PPS events generation. Platform/board specific.
-
-References:
- Documentation/devicetree/bindings/clock/ti,sci-clk.txt
- Documentation/devicetree/bindings/clock/clock-bindings.txt
- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
- Documentation/devicetree/bindings/interrupt-controller/ti,sci-irq.txt
-
-Examples:
-
-Main CPTS module:
-cpts@310d0000 {
- compatible = "ti,am65-cpts";
- reg = <0x0 0x310d0000 0x0 0x400>;
- reg-names = "cpts";
- clocks = <&main_cpts_mux>;
- clock-names = "cpts";
- interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-periodic-outputs = <6>;
- ti,cpts-ext-ts-inputs = <8>;
-
- main_cpts_mux: refclk-mux {
- #clock-cells = <0>;
- clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
- <&k3_clks 157 91>, <&k3_clks 157 77>,
- <&k3_clks 157 102>, <&k3_clks 157 80>,
- <&k3_clks 120 3>, <&k3_clks 121 3>;
- assigned-clocks = <&main_cpts_mux>;
- assigned-clock-parents = <&k3_clks 118 11>;
- };
-};
-
-MCU CPSW CPTS module:
-mcu_cpsw: cpsw_nuss@046000000 {
- compatible = "ti,am654-cpsw-nuss";
- [...]
-
- cpts {
- clocks = <&mcu_cpsw_cpts_mux>;
- clock-names = "cpts";
- interrupts-extended = <&gic GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cpts";
- ti,cpts-ext-ts-inputs = <4>;
- ti,cpts-periodic-outputs = <2>;
-
- mcu_cpsw_cpts_mux: refclk-mux {
- #clock-cells = <0>;
- clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
- <&k3_clks 157 91>, <&k3_clks 157 77>,
- <&k3_clks 157 102>, <&k3_clks 157 80>,
- <&k3_clks 120 3>, <&k3_clks 121 3>;
- assigned-clocks = <&mcu_cpsw_cpts_mux>;
- assigned-clock-parents = <&k3_clks 118 11>;
- };
- };
-};
+This file has moved to ti,k3-am654-cpts.yaml.
diff --git a/Documentation/devicetree/bindings/net/ti,davinci-mdio.yaml b/Documentation/devicetree/bindings/net/ti,davinci-mdio.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..a1cd0e69c3ddc1b15d43caa83a6cdbf1ce4c0b41
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,davinci-mdio.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/ti,davinci-mdio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI SoC Davinci/Keystone2 MDIO Controller
+
+maintainers:
+ - Grygorii Strashko <grygorii.strashko@ti.com>
+
+description:
+ TI SoC Davinci/Keystone2 MDIO Controller
+
+allOf:
+ - $ref: "mdio.yaml#"
+
+properties:
+ compatible:
+ oneOf:
+ - const: ti,davinci_mdio
+ - items:
+ - const: ti,keystone_mdio
+ - const: ti,davinci_mdio
+ - items:
+ - const: ti,cpsw-mdio
+ - const: ti,davinci_mdio
+ - items:
+ - const: ti,am4372-mdio
+ - const: ti,cpsw-mdio
+ - const: ti,davinci_mdio
+
+ reg:
+ maxItems: 1
+
+ bus_freq:
+ maximum: 2500000
+ description: MDIO Bus frequency
+
+ ti,hwmods:
+ description: TI hwmod name
+ deprecated: true
+ $ref: /schemas/types.yaml#/definitions/string-array
+ items:
+ const: davinci_mdio
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: ti,davinci_mdio
+
+then:
+ required:
+ - bus_freq
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ davinci_mdio: mdio@4a101000 {
+ compatible = "ti,davinci_mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4a101000 0x1000>;
+ bus_freq = <1000000>;
+ };
diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..0d992ff5db8ea0b8f9bddd4f5efb92ba8ac23086
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
@@ -0,0 +1,259 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller) Device Tree Bindings
+
+maintainers:
+ - Grygorii Strashko <grygorii.strashko@ti.com>
+ - Sekhar Nori <nsekhar@ti.com>
+
+description:
+ The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
+ (one external) and provides Ethernet packet communication for the device.
+ The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
+ (two external) and provides Ethernet packet communication and switching.
+
+ The internal Communications Port Programming Interface (CPPI5) (Host port 0).
+ Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
+ and one RX channels and operating by NAVSS Unified DMA Peripheral Root
+ Complex (UDMA-P) controller.
+
+ CPSWxG features
+ updated Address Lookup Engine (ALE).
+ priority level Quality Of Service (QOS) support (802.1p)
+ Support for Audio/Video Bridging (P802.1Qav/D6.0)
+ Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
+ Flow Control (802.3x) Support
+ Time Sensitive Network Support
+ IEEE P902.3br/D2.0 Interspersing Express Traffic
+ IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
+ Configurable number of addresses plus VLANs
+ Configurable number of classifier/policers
+ VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
+ ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
+ RX/TX csum offload
+ Management Data Input/Output (MDIO) interface for PHYs management
+ RMII/RGMII Interfaces support
+ new version of Common Platform Time Sync (CPTS)
+
+ The CPSWxG NUSS is integrated into
+ device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.
+ device MAIN domain named CPSW0 on AM642x SoC.
+
+ Specifications can be found at
+ https://www.ti.com/lit/pdf/spruid7
+ https://www.ti.com/lit/zip/spruil1
+ https://www.ti.com/lit/pdf/spruim2
+
+properties:
+ "#address-cells": true
+ "#size-cells": true
+
+ compatible:
+ oneOf:
+ - const: ti,am654-cpsw-nuss
+ - const: ti,j721e-cpsw-nuss
+ - const: ti,am64-cpsw-nuss
+
+ reg:
+ maxItems: 1
+ description:
+ The physical base address and size of full the CPSWxG NUSS IO range
+
+ reg-names:
+ items:
+ - const: cpsw_nuss
+
+ ranges: true
+
+ dma-coherent: true
+
+ clocks:
+ maxItems: 1
+ description: CPSWxG NUSS functional clock
+
+ clock-names:
+ items:
+ - const: fck
+
+ assigned-clock-parents: true
+
+ assigned-clocks: true
+
+ power-domains:
+ maxItems: 1
+
+ dmas:
+ maxItems: 9
+
+ dma-names:
+ items:
+ - const: tx0
+ - const: tx1
+ - const: tx2
+ - const: tx3
+ - const: tx4
+ - const: tx5
+ - const: tx6
+ - const: tx7
+ - const: rx
+
+ ethernet-ports:
+ type: object
+ properties:
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+
+ patternProperties:
+ port@[1-2]:
+ type: object
+ description: CPSWxG NUSS external ports
+
+ $ref: ethernet-controller.yaml#
+
+ properties:
+ reg:
+ minimum: 1
+ maximum: 2
+ description: CPSW port number
+
+ phys:
+ maxItems: 1
+ description: phandle on phy-gmii-sel PHY
+
+ label:
+ description: label associated with this port
+
+ ti,mac-only:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Specifies the port works in mac-only mode.
+
+ ti,syscon-efuse:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandle to the system control device node which provides access
+ to efuse IO range with MAC addresses
+
+ required:
+ - reg
+ - phys
+
+ additionalProperties: false
+
+patternProperties:
+ "^mdio@[0-9a-f]+$":
+ type: object
+ $ref: "ti,davinci-mdio.yaml#"
+
+ description:
+ CPSW MDIO bus.
+
+ "^cpts@[0-9a-f]+":
+ type: object
+ $ref: "ti,k3-am654-cpts.yaml#"
+ description:
+ CPSW Common Platform Time Sync (CPTS) module.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - ranges
+ - clocks
+ - clock-names
+ - power-domains
+ - dmas
+ - dma-names
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/pinctrl/k3.h>
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+ #include <dt-bindings/net/ti-dp83867.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mcu_cpsw: ethernet@46000000 {
+ compatible = "ti,am654-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
+ dma-coherent;
+ clocks = <&k3_clks 5 10>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+
+ dmas = <&mcu_udmap 0xf000>,
+ <&mcu_udmap 0xf001>,
+ <&mcu_udmap 0xf002>,
+ <&mcu_udmap 0xf003>,
+ <&mcu_udmap 0xf004>,
+ <&mcu_udmap 0xf005>,
+ <&mcu_udmap 0xf006>,
+ <&mcu_udmap 0xf007>,
+ <&mcu_udmap 0x7000>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ ti,syscon-efuse = <&mcu_conf 0x200>;
+ phys = <&phy_gmii_sel 1>;
+
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&phy0>;
+ };
+ };
+
+ davinci_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 5 10>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+ };
+ };
+
+ cpts@3d000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 18 2>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..4111aa3cd035499b8733758ce6e9024cce3e76bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/ti,k3-am654-cpts.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: The TI AM654x/J721E Common Platform Time Sync (CPTS) module Device Tree Bindings
+
+maintainers:
+ - Grygorii Strashko <grygorii.strashko@ti.com>
+ - Sekhar Nori <nsekhar@ti.com>
+
+description: |+
+ The TI AM654x/J721E CPTS module is used to facilitate host control of time
+ sync operations.
+ Main features of CPTS module are
+ - selection of multiple external clock sources
+ - Software control of time sync events via interrupt or polling
+ - 64-bit timestamp mode in ns with PPM and nudge adjustment.
+ - hardware timestamp push inputs (HWx_TS_PUSH)
+ - timestamp counter compare output (TS_COMP)
+ - timestamp counter bit output (TS_SYNC)
+ - periodic Generator function outputs (TS_GENFx)
+ - Ethernet Enhanced Scheduled Traffic Operations (CPTS_ESTFn) (TSN)
+ - external hardware timestamp push inputs (HWx_TS_PUSH) timestamping
+
+ Depending on integration it enables compliance with the IEEE 1588-2008
+ standard for a precision clock synchronization protocol, Ethernet Enhanced
+ Scheduled Traffic Operations (CPTS_ESTFn) and PCIe Subsystem Precision Time
+ Measurement (PTM).
+
+ TI AM654x/J721E SoCs has several similar CPTS modules integrated into the
+ different parts of the system which could be synchronized with each other
+ - Main CPTS
+ - MCU CPSW CPTS with IEEE 1588-2008 support
+ - PCIe subsystem CPTS for PTM support
+
+ Depending on CPTS module integration and when CPTS is integral part of
+ another module (MCU CPSW for example) "compatible" and "reg" can
+ be omitted - parent module is fully responsible for CPTS enabling and
+ configuration.
+
+properties:
+ $nodename:
+ pattern: "^cpts@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - const: ti,am65-cpts
+ - const: ti,j721e-cpts
+
+ reg:
+ maxItems: 1
+ description:
+ The physical base address and size of CPTS IO range
+
+ reg-names:
+ items:
+ - const: cpts
+
+ clocks:
+ maxItems: 1
+ description: CPTS reference clock
+
+ clock-names:
+ items:
+ - const: cpts
+
+ interrupts:
+ items:
+ - description: CPTS events interrupt
+
+ interrupt-names:
+ items:
+ - const: cpts
+
+ assigned-clock-parents: true
+
+ assigned-clocks: true
+
+ power-domains:
+ maxItems: 1
+
+ ti,cpts-ext-ts-inputs:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 8
+ description:
+ Number of hardware timestamp push inputs (HWx_TS_PUSH)
+
+ ti,cpts-periodic-outputs:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 8
+ description:
+ Number of timestamp Generator function outputs (TS_GENFx)
+
+ ti,pps:
+ allOf:
+ - $ref: /schemas/types.yaml#definitions/uint32-array
+ - minItems: 2
+ maxItems: 2
+ description:
+ The pair of HWx_TS_PUSH input and TS_GENFy output indexes used for
+ PPS events generation. Platform/board specific.
+
+ refclk-mux:
+ type: object
+ description: CPTS reference clock multiplexer clock
+ properties:
+ '#clock-cells':
+ const: 0
+
+ clocks:
+ maxItems: 8
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clocks-parents:
+ maxItems: 1
+
+ required:
+ - clocks
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ cpts@310d0000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x310d0000 0x400>;
+ reg-names = "cpts";
+ clocks = <&main_cpts_mux>;
+ clock-names = "cpts";
+ interrupts-extended = <&k3_irq 163 0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-periodic-outputs = <6>;
+ ti,cpts-ext-ts-inputs = <8>;
+
+ main_cpts_mux: refclk-mux {
+ #clock-cells = <0>;
+ clocks = <&k3_clks 118 5>, <&k3_clks 118 11>,
+ <&k3_clks 157 91>, <&k3_clks 157 77>,
+ <&k3_clks 157 102>, <&k3_clks 157 80>,
+ <&k3_clks 120 3>, <&k3_clks 121 3>;
+ assigned-clocks = <&main_cpts_mux>;
+ assigned-clock-parents = <&k3_clks 118 11>;
+ };
+ };