From a36edbf3d88e66d394a2fda5762197192e835666 Mon Sep 17 00:00:00 2001
From: Pratyush Yadav <p.yadav@ti.com>
Date: Thu, 18 Feb 2021 17:39:39 +0530
Subject: [PATCH] arm64: dts: ti: k3-j721e: Add nodes to enable CSI2
Add nodes for Cadence CSI2RX, DPHY, and TI's CSI2RX wrapper. Also add
nodes for OV5640 which is the camera the drivers have been tested with.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
.../dts/ti/k3-j721e-common-proc-board.dts | 32 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 32 +++++++++++++++++++
2 files changed, 64 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index d1a2eb4153b05..7d4b2a7b21308 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -161,6 +161,12 @@ dp_connector_in: endpoint {
};
};
};
+
+ clk_ov5640_fixed: ov5640-xclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
};
&main_pmx0 {
@@ -726,6 +732,23 @@ exp5: gpio@20 {
gpio-controller;
#gpio-cells = <2>;
};
+
+ ov5640: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+
+ clocks = <&clk_ov5640_fixed>;
+ clock-names = "xclk";
+ reset-gpios = <&exp5 0 GPIO_ACTIVE_LOW>;
+
+ port {
+ csi2_cam0: endpoint {
+ remote-endpoint = <&csi2rx0_in_sensor>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
};
&mcasp10 {
@@ -999,3 +1022,12 @@ &main_mcan12 {
&main_mcan13 {
status = "disabled";
};
+
+&csi2_0 {
+ csi2rx0_in_sensor: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 3580d2d9f6d0d..8d0c16252ffa7 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -2422,4 +2422,36 @@ main_mcan13: can@27d1000 {
bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
};
+ ti_csi2rx0: ticsi2rx@4500000 {
+ compatible = "ti,csi2rx";
+ dmas = <&main_udmap 0x4940>;
+ dma-names = "rx0";
+ reg = <0x0 0x4500000 0x0 0x1000>;
+ power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cdns_csi2rx: csi-bridge@4504000 {
+ compatible = "cdns,csi2rx";
+ reg = <0x0 0x4504000 0x0 0x1000>;
+ clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
+ <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ ports {
+ csi2_0: port { };
+ };
+ };
+ };
+
+ dphy0: phy@4580000 {
+ compatible = "cdns,dphy";
+ reg = <0x0 0x4580000 0x0 0x1100>;
+ #phy-cells = <0>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ };
};
--
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