diff --git a/boards/beaglebone/ai-64/ch06.rst b/boards/beaglebone/ai-64/ch06.rst deleted file mode 100644 index 22a616fbe05d6040db5842de940c2a8896faab7a..0000000000000000000000000000000000000000 --- a/boards/beaglebone/ai-64/ch06.rst +++ /dev/null @@ -1,1758 +0,0 @@ -:orphan: - -.. _detailed-hardware-design: - -Detailed Hardware Design -######################### - -This section provides a detailed description of the Hardware design. -This can be useful for interfacing, writing drivers, or using it to help -modify specifics of your own design. - -:ref:`bbai-64-block-diagram-ch06` below is the high level block diagram of the board. For those who may be concerned, It is the same figure as shown in :ref:`beaglebone-ai-64-high-level-specification`. It is placed here again for convenience so it is closer to the topics to follow. - -.. _bbai-64-block-diagram-ch06: - -.. figure:: images/ch05/board-block-diagram.svg - :width: 400px - :align: center - :alt: Fig: BeagleBone AI-64 Key Components - - Fig: BeagleBone AI-64 Key Components - -.. _power-section: - -Power Section ------------------------------------ - -:ref:`power-flow-diagram` shows the high level block diagram of the power section of the board. - -.. _power-flow-diagram,High level power block diagram: - -.. figure:: images/ch06/power.svg - :width: 400px - :align: center - :alt: Fig: High level power block diagram - - Fig: High level power block diagram - -This section describes the power section of the design and all the -functions performed by the *TPS65941213 and TPS65941111*. - -.. _TPS65941213-and-TPS65941111-pmic: - -TPS65941213 and TPS65941111 PMIC -********************************************* - -The main Power Management IC (PMIC) in the system is the *TPS65941213 and TPS65941111* -which is a single chip power management IC consisting of a linear -dual-input power path, three step-down converters, and four LDOs. LDO -stands for Low Drop Out. If you want to know more about an LDO, you can -go to `http://en.wikipedia.org/wiki/Low-dropout_regulator <http://en.wikipedia.org/wiki/Low-dropout_regulator>`_ . - -If you want to learn more about step-down converters, you can go to `_http://en.wikipedia.org/wiki/DC-to-DC_converter <http://en.wikipedia.org/wiki/DC-to-DC_converter>`_ . - -The system is supplied by a USB port or DC adapter. Three -high-efficiency 2.25MHz step-down converters are targeted at providing -the core voltage, MPU, and memory voltage for the board. - -The step-down converters enter a low power mode at light load for -maximum efficiency across the widest possible range of load currents. -For low-noise applications the devices can be forced into fixed -frequency PWM using the I2C interface. The step-down converters allow -the use of small inductors and capacitors to achieve a small footprint -solution size. - -LDO1 and LDO2 are intended to support system standby mode. In normal -operation, they can support up to 100mA each. LDO3 and LDO4 can support -up to 285mA each. - -By default only LDO1 is always ON but any rail can be configured to -remain up in SLEEP state. In particular the DCDC converters can remain -up in a low-power PFM mode to support processor suspend mode. The -*TPS65941213 and TPS65941111* offers flexible power-up and power-down sequencing and -several house-keeping functions such as power-good output, pushbutton -monitor, hardware reset function and temperature sensor to protect the -battery. - -See the :ref:`TPS6594-Q1-block-diagram` shown below for high level details -for *TPS65941213 and TPS65941111*, for more information on the, refer to https://www.ti.com/product/TPS6594-Q1 Texas instruments product page. - -.. _TPS6594-Q1-block-diagram: - -.. figure:: images/ch06/TPS6594-Q1.svg - :width: 400px - :align: center - :alt: Fig: TPS6594-Q1 block diagram - - Fig: TPS6594-Q1 block diagram - -.. _pmic-a-diagram,PMIC-A TPS65941213 circuit: - -.. figure:: images/ch06/pmic-a.svg - :width: 400px - :align: center - :alt: Fig: PMIC-B TPS65941213 circuit - - Fig: PMIC-B TPS65941213 circuit - -.. _pmic-b-diagram,PMIC-B TPS65941111 circuit: - -.. figure:: images/ch06/pmic-b.svg - :width: 400px - :align: center - :alt: Fig: PMIC-B TPS65941111 circuit - - Fig: PMIC-B TPS65941111 circuit - -.. _dc-input: - -DC Input -*********** - -:ref:`figure-23` below shows how the DC input is connected to the **TPS65941213 and TPS65941111**. - -.. _figure-23,Figure 23: - -.. figure:: media/image38.png - :width: 400px - :align: center - :alt: Fig: TPS65217 DC Connection - - Fig: TPS65217 DC Connection - -A 5VDC supply can be used to provide power to the board. The power -supply current depends on how many and what type of add-on boards are -connected to the board. For typical use, a 5VDC supply rated at 1A -should be sufficient. If heavier use of the expansion headers or USB -host port is expected, then a higher current supply will be required. - -The connector used is a 2.1MM center positive x 5.5mm outer barrel. The -5VDC rail is connected to the expansion header. It is possible to power -the board via the expansion headers from an add-on card. The 5VDC is -also available for use by the add-on cards when the power is supplied by -the 5VDC jack on the board. - -.. _usb-power: - -USB Power -************* - -The board can also be powered from the USB port. A typical USB port is -limited to 500mA max. When powering from the USB port, the VDD_5V rail -is not provided to the expansion headers, so capes that require the 5V -rail to supply the cape direct, bypassing the *TPS65941213 and TPS65941111*, will not have -that rail available for use. The 5VDC supply from the USB port is -provided on the SYS_5V, the one that comes from the**TPS65941213 and TPS65941111**, rail -of the expansion header for use by a cape. *Figure 24* is the connection -of the USB power input on the PMIC. - -.. _figure-24.-usb-power-connections: - -.. figure:: media/image96.png - :width: 400px - :align: center - :alt: Fig: USB Power Connections - - Fig: USB Power Connections - - - -.. _power-selection: - -Power Selection -********************************************* - -The selection of either the 5VDC or the USB as the power source is -handled internally to the *TPS65941213 and TPS65941111* and automatically switches to 5VDC -power if both are connected. SW can change the power configuration via -the I2C interface from the processor. In addition, the SW can read -the**TPS65941213 and TPS65941111** and determine if the board is running on the 5VDC input -or the USB input. This can be beneficial to know the capability of the -board to supply current for things like operating frequency and -expansion cards. - -It is possible to power the board from the USB input and then connect -the DC power supply. The board will switch over automatically to the DC -input. - -.. _power-button-1: - -Power Button -********************************************* - -A power button is connected to the input of the *TPS65941213 and TPS65941111*. This is a -momentary switch, the same type of switch used for reset and boot -selection on the board. - -If you push the button the *TPS65941213 and TPS65941111* will send an interrupt to the -processor. It is up to the processor to then pull the**PMIC_POWER_EN** -pin low at the correct time to power down the board. At this point, the -PMIC is still active, assuming that the power input was not removed. -Pressing the power button will cause the board to power up again if the -processor puts the board in the power off mode. - -In power off mode, the RTC rail is still active, keeping the RTC powered -and running off the main power input. If you remove that power, then the -RTC will not be powered. You also have the option of using the battery -holes on the board to connect a battery if desired as discussed in the -next section. - -If you push and hold the button for greater than 8 seconds, the PMIC -will power down. But you must release the button when the power LED -turns off. Holding the button past that point will cause the board to -power cycle. - -.. _section-6-1-7,Section 6.1.7 Power Consumption: - -Power Consumption -********************************************* - -The power consumption of the board varies based on power scenarios and -the board boot processes. Measurements were taken with the board in the -following configuration: - -* DC powered and USB powered -* monitor connected -* USB HUB -* 4GB USB flash drive -* Ethernet connected @ 100M -* Serial debug cable connected - -:ref:`table-4` is an analysis of the power consumption of the board in these various scenarios. - -.. _table-4,Table 4: - -.. list-table:: Table 2: BeagleBone AI-64 Features and Specification - :header-rows: 1 - - * - MODE - - USB - - DC - - C+USB - * - Reset - - TBD - - TBD - - TBD - * - Idling @ UBoot - - 210 - - 210 - - 210 - * - Kernel Booting (Peak) - - 460 - - 460 - - 460 - * - Kernel Idling - - 350 - - 350 - - 350 - * - Kernel Idling Display Blank - - 280 - - 280 - - 280 - * - Loading a Webpage - - 430 - - 430 - - 430 - -The current will fluctuate as various activates occur, such as the LEDs -on and microSD/eMMC accesses. - -.. _processor-interfaces: - -Processor Interfaces -********************************************* - -The processor interacts with the *TPS65941213 and TPS65941111* via several different -signals. Each of these signals is described below. - -.. _i2c0: - -I2C0 -************ - -I2C0 is the control interface between the processor and the *TPS65941213 and TPS65941111*. -It allows the processor to control the registers inside the**TPS65941213 and TPS65941111** -for such things as voltage scaling and switching of the input rails. - -.. _pmc_powr_en: - -PMIC_POWR_EN -****************** - -On power up the *VDD_RTC* rail activates first. After the RTC circuitry -in the processor has activated it instructs the**TPS65941213 and TPS65941111** to initiate -a full power up cycle by activating the *PMIC_POWR_EN* signal by taking -it HI. When powering down, the processor can take this pin low to start -the power down process. - -.. _ldo_good: - -LDO_GOOD -********************* - -This signal connects to the *RTC_PORZn* signal, RTC power on reset. The -small “*n*†indicates that the signal is an active low signal. Word -processors seem to be unable to put a bar over a word so the**n** is -commonly used in electronics. As the RTC circuitry comes up first, this -signal indicates that the LDOs, the 1.8V VRTC rail, is up and stable. -This starts the power up process. - -.. _pmic_pgood: - -PMIC_PGOOD -****************** - -Once all the rails are up, the *PMIC_PGOOD* signal goes high. This -releases the**PORZn** signal on the processor which was holding the -processor reset. - -.. _wakeup: - -WAKEUP -************** - -The WAKEUP signal from the *TPS65941213 and TPS65941111* is connected to the**EXT_WAKEUP** -signal on the processor. This is used to wake up the processor when it -is in a sleep mode. When an event is detected by the *TPS65941213 and TPS65941111*, such -as the power button being pressed, it generates this signal. - -.. _pmic_int: - -PMIC_INT -************ - -The *PMIC_INT* signal is an interrupt signal to the processor. Pressing -the power button will send an interrupt to the processor allowing it to -implement a power down mode in an orderly fashion, go into sleep mode, -or cause it to wake up from a sleep mode. All of these require SW -support. - -.. _power-rails: - -6.1.9 Power Rails -*********************** - -:ref:`figure-25` shows the connections of each of the rails from the **TPS65941213 and TPS65941111**. - -.. _figure-25,Figure 25: - -.. figure:: media/image39.jpg - :width: 400px - :align: center - :alt: fig-25: Power Rails - - Fig-25: Power Rails - -VRTC Rail -************ - -The *VRTC* rail is a 1.8V rail that is the first rail to come up in the -power sequencing. It provides power to the RTC domain on the processor -and the I/O rail of the **TPS65941213 and TPS65941111**. It can deliver up to 250mA -maximum. - -VDD_3V3A Rail -************************* - -The *VDD_3V3A* rail is supplied by the **TPS65941213 and TPS65941111** and provides the -3.3V for the processor rails and can provide up to 400mA. - -VDD_3V3B Rail -********************** - -The current supplied by the *VDD_3V3A* rail is not sufficient to power -all of the 3.3V rails on the board. So a second LDO is supplied, U4, -a **TL5209A**, which sources the *VDD_3V3B* rail. It is powered up just -after the *VDD_3V3A* rail. - -VDD_1V8 Rail -********************************************* - -The *VDD_1V8* rail can deliver up to 400mA and provides the power -required for the 1.8V rails on the processor and the display framer. This -rail is not accessible for use anywhere else on the board. - -VDD_CORE Rail -********************************************* - -The *VDD_CORE* rail can deliver up to 1.2A at 1.1V. This rail is not -accessible for use anywhere else on the board and connects only to the -processor. This rail is fixed at 1.1V and should not be adjusted by SW -using the PMIC. If you do, then the processor will no longer work. - -VDD_MPU Rail -********************************************* - -The *VDD_MPU* rail can deliver up to 1.2A. This rail is not accessible -for use anywhere else on the board and connects only to the processor. -This rail defaults to 1.1V and can be scaled up to allow for higher -frequency operation. Changing of the voltage is set via the I2C -interface from the processor. - -VDDS_DDR Rail -********************************************* - -The *VDDS_DDR* rail defaults to**1.5V** to support the LPDDR4 rails and -can deliver up to 1.2A. It is possible to adjust this voltage rail down -to *1.35V* for lower power operation of the LPDDR4 device. Only LPDDR4 -devices can support this voltage setting of 1.35V. - -Power Sequencing -********************************************* - -The power up process is consists of several stages and events. :ref:`figure-26` -describes the events that make up the power up process for the -processer from the PMIC. This diagram is used elsewhere to convey -additional information. I saw no need to bust it up into smaller -diagrams. It is from the processor datasheet supplied by Texas -Instruments. - -.. _figure-26,Figure 26: - -.. figure:: media/image40.png - :width: 400px - :align: center - :alt: Fig-26: Power Rail Power Up Sequencing - - Fig-26: Power Rail Power Up Sequencing - -:ref:`figure-27` the voltage rail sequencing for the**TPS65941213 and TPS65941111** as it -powers up and the voltages on each rail. The power sequencing starts at -15 and then goes to one. That is the way the *TPS65941213 and TPS65941111* is configured. -You can refer to the TPS65941213 and TPS65941111 datasheet for more information. - -.. _figure-27,Figure 27: - -.. figure:: media/image41.png - :width: 400px - :align: center - :alt: Fig-27: TPS65941213 and TPS65941111 Power Sequencing Timing - - Fig-27: TPS65941213 and TPS65941111 Power Sequencing Timing - -.. _power-led: - -Power LED -********************************************* - -The power LED is a blue LED that will turn on once the *TPS65941213 and TPS65941111* has -finished the power up procedure. If you ever see the LED flash once, -that means that the**TPS65941213 and TPS65941111** started the process and encountered an -issue that caused it to shut down. The connection of the LED is shown in -:ref:`figure-25`. - -.. _TPS65941213-and-TPS65941111-power-up-process: - -TPS65941213 and TPS65941111 Power Up Process -********************************************* - -:ref:`figure-28` shows the interface between the **TPS65941213 and TPS65941111** and the -processor. It is a cut from the PDF form of the schematic and reflects -what is on the schematic. - -.. _figure-28,Figure 28: - -.. figure:: media/image42.jpg - :width: 400px - :align: center - :alt: Fig-28: Power Processor Interfaces - -When voltage is applied, DC or USB, the *TPS65941213 and TPS65941111* connects the power -to the SYS output pin which drives the switchers and LDOs in -the **TPS65941213 and TPS65941111**. - -At power up all switchers and LDOs are off except for the *VRTC LDO* -(1.8V), which provides power to the VRTC rail and controls -the **RTC_PORZn** input pin to the processor, which starts the power up -process of the processor. Once the RTC rail powers up, the *RTC_PORZn* -pin, driven by the *LDO_PGOOD* signal from the *TPS65941213 and TPS65941111*, of the -processor is released. - -Once the *RTC_PORZn* reset is released, the processor starts the -initialization process. After the RTC stabilizes, the processor launches -the rest of the power up process by activating the**PMIC_POWER_EN** -signal that is connected to the *TPS65941213 and TPS65941111* which starts the *TPS65941213 and TPS65941111* -power up process. - -The *LDO_PGOOD* signal is provided by the**TPS65941213 and TPS65941111** to the processor. -As this signal is 1.8V from the *TPS65941213 and TPS65941111* by virtue of the *TPS65941213 and TPS65941111* -VIO rail being set to 1.8V, and the *RTC_PORZ* signal on the processor -is 3.3V, a voltage level shifter, *U4*, is used. Once the LDOs and -switchers are up on the *TPS65941213 and TPS65941111*, this signal goes active releasing -the processor. The LDOs on the *TPS65941213 and TPS65941111* are used to power the VRTC -rail on the processor. - -.. _processor-control-interface: - -Processor Control Interface -********************************************* - -:ref:`figure-28` above shows two interfaces between the processor and -the**TPS65941213 and TPS65941111** used for control after the power up sequence has -completed. - -The first is the *I2C0* bus. This allows the processor to turn on and -off rails and to set the voltage levels of each regulator to supports -such things as voltage scaling. - -The second is the interrupt signal. This allows the *TPS65941213 and TPS65941111* to alert -the processor when there is an event, such as when the power button is -pressed. The interrupt is an open drain output which makes it easy to -interface to 3.3V of the processor. - -.. _low-power-mode-support: - -Low Power Mode Support -********************************************* - -This section covers three general power down modes that are available. -These modes are only described from a Hardware perspective as it relates -to the HW design. - -RTC Only -********************************************* - -In this mode all rails are turned off except the *VDD_RTC*. The -processor will need to turn off all the rails to enter this mode. -The **VDD_RTC** staying on will keep the RTC active and provide for the -wakeup interfaces to be active to respond to a wake up event. - -RTC Plus DDR -********************************************* - -In this mode all rails are turned off except the *VDD_RTC* and -the **VDDS_DDR**, which powers the LPDDR4 memory. The processor will need -to turn off all the rails to enter this mode. The *VDD_RTC* staying on -will keep the RTC active and provide for the wakeup interfaces to be -active to respond to a wake up event. - -The *VDDS_DDR* rail to the LPDDR4 is provided by the 1.5V rail of -the **TPS65941213 and TPS65941111** and with *VDDS_DDR* active, the LPDDR4 can be placed in -a self refresh mode by the processor prior to power down which allows -the memory data to be saved. - -Currently, this feature is not included in the standard software -release. The plan is to include it in future releases. - -Voltage Scaling -********************************************* - -For a mode where the lowest power is possible without going to sleep, -this mode allows the voltage on the ARM processor to be lowered along -with slowing the processor frequency down. The I2C0 bus is used to -control the voltage scaling function in the *TPS65941213 and TPS65941111*. - -.. _sitara-am3358bzcz100-processor: - -TI J721E DRA829/TDA4VM/AM752x Processor ------------------------------------------ - -The board is designed to use the TI J721E DRA829/TDA4VM/AM752x processor in the -15 x 15 package. - -.. _description: - -Description -********************************************* - -:ref:`figure-29` is a high level block diagram of the processor. For more information on the processor, go to `https://www.ti.com/product/TDA4VM <https://www.ti.com/product/TDA4VM>`_ - -.. _figure-29,Figure 29: - -.. figure:: media/image43.png - :width: 400px - :align: center - :alt: Fig-29: Jacinto TDA4VMBZCZ Block Diagram - - Fig-29: Jacinto TDA4VMBZCZ Block Diagram - - -.. _high-level-features: - -High Level Features -********************************************* - -:ref:`table-5` below shows a few of the high level features of the Jacinto -processor. - -.. _table-5,Table 5: - - -.. list-table:: Table 5: Processor Features - :header-rows: 1 - - * - Operating Systems - - Linux, Android, Windows Embedded CE,QNX,ThreadX - - MMC/SD - - 3 - * - Standby Power - - 7 mW - - CAN - - 2 - * - ARM CPU - - 1 ARM Cortex-A8 - - UART (SCI) - - 6 - * - ARM MHz (Max.) - - 275,500,600,800,1000 - - ADC - - 8-ch 12-bit - * - ARM MIPS (Max.) - - 1000,1200,2000 - - PWM (Ch) - - 3 - * - Graphics Acceleration - - 1 3D - - eCAP - - 3 - * - Other Hardware Acceleration - - 2 PRU-ICSS,Crypto Accelerator - - eQEP - - 3 - * - On-Chip L1 Cache - - 64 KB (ARM Cortex-A8) - - RTC - - 1 - * - On-Chip L2 Cache - - 256 KB (ARM Cortex-A8) - - I2C - - 3 - * - Other On-Chip Memory - - 128 KB - - McASP - - 2 - * - Display Options - - LCD - - SPI - - 2 - * - General Purpose Memory - - 1 16-bit (GPMC, NAND flash, NOR Flash, SRAM) - - DMA (Ch) - - 64-Ch EDMA - * - DRAM - - 1 16-bit (LPDDR-400,DDR2-532, DDR3-400) - - IO Supply (V) - - 1.8V(ADC),3.3V - * - USB Ports - - 2 - - Operating Temperature Range (C) - - -40 to 90 - -.. _documentation: - -Documentation -********************** - -Full documentation for the processor can be found on the TI website at `https://www.ti.com/product/TDA4VM <https://www.ti.com/product/TDA4VM>`_ for the current processor used on the board. Make sure that you always use the latest datasheets and Technical Reference Manuals (TRM). - -.. _crystal-circuitry: - -Crystal Circuitry -*********************** - -:ref:`figure-30` is the crystal circuitry for the TDA4VM processor. - -.. _figure-30,Figure 30: - -.. figure:: media/image44.png - :width: 400px - :align: center - :alt: Fig-30: Processor Crystals - - Fig-30: Processor Crystals - -.. _reset-circuitry: - -Reset Circuitry -********************************************* - -:ref:`figure-31` is the board reset circuitry. The initial power on reset is -generated by the **TPS65941213 and TPS65941111** power management IC. It also handles the -reset for the Real Time Clock. - -The board reset is the SYS_RESETn signal. This is connected to the -NRESET_INOUT pin of the processor. This pin can act as an input or an -output. When the reset button is pressed, it sends a warm reset to the -processor and to the system. - -On the revision A5D board, a change was made. On power up, the -NRESET_INOUT signal can act as an output. In this instance it can cause -the SYS_RESETn line to go high prematurely. In order to prevent this, -the PORZn signal from the TPS65941213 and TPS65941111 is connected to the SYS_RESETn line -using an open drain buffer. These ensure that the line does not -momentarily go high on power up. - -.. _figure-31,Figure 31: - -.. figure:: media/image45.png - :width: 400px - :align: center - :alt: Fig-31: Board Reset Circuitry - - Fig-31: Board Reset Circuitry - -This change is also in all revisions after A5D. - -LPDDR4 Memory - -BeagleBone AI-64 uses a single MT41K256M16HA-125 512MB LPDDR4 device -from Micron that interfaces to the processor over 16 data lines, 16 -address lines, and 14 control lines. On rev C we added the Kingston -*KE4CN2H5A-A58* device as a source for the LPDDR4 device. - -The following sections provide more details on the design. - -.. _memory-device: - -Memory Device -********************************************* - -The design supports the standard DDR3 and LPDDR4 x16 devices and is built -using the LPDDR4. A single x16 device is used on the board and there is -no support for two x8 devices. The DDR3 devices work at 1.5V and the -LPDDR4 devices can work down to 1.35V to achieve lower power. The LPDDR4 comes in a 96-BALL FBGA package -with 0.8 mil pitch. Other standard DDR3 devices can also be supported, -but the LPDDR4 is the lower power device and was chosen for its ability -to work at 1.5V or 1.35V. The standard frequency that the LPDDR4 is run -at on the board is 400MHZ. - -.. _ddr3l-memory-design: - -LPDDR4 Memory Design -********************************************* - -:ref:`figure-32` is the schematic for the LPDDR4 memory device. Each of the -groups of signals is described in the following lines. - -*Address Lines:* Provide the row address for ACTIVATE commands, and the -column address and auto pre-charge bit (A10) for READ/WRITE commands, to -select one location out of the memory array in the respective bank. A10 -sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address -inputs also provide the op-code during a LOAD MODE command. Address -inputs are referenced to VREFCA. A12/BC#: When enabled in the mode -register (MR), A12 is sampled during READ and WRITE commands to -determine whether burst chop (on-the-fly) will be performed (HIGH BL8 -or no burst chop, LOW BC4 burst chop). - -*Bank Address Lines:* BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. - -*CK and CK# Lines:* are differential clock inputs. All address and -control input signals are sampled on the crossing of the positive edge -of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is -referenced to the crossings of CK and CK#. - -*Clock Enable Line:* CKE enables (registered HIGH) and disables -(registered LOW) internal circuitry and clocks on the DRAM. The specific -circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM -configuration and operating mode. Taking CKE LOW provides PRECHARGE -power-down and SELF REFRESH operations (all banks idle) or active -power-down (row active in any bank). CKE is synchronous for powerdown -entry and exit and for self refresh entry. CKE is asynchronous for self -refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) -are disabled during powerdown. Input buffers (excluding CKE and RESET#) -are disabled during SELF REFRESH. CKE is referenced to VREFCA. - -.. _figure-32,Figure 32: - -.. figure:: media/image46.png - :width: 400px - :align: center - :alt: Fig-32: LPDDR4 Memory Design - - Fig-32: LPDDR4 Memory Design - -*Chip Select Line:* CS# enables (registered LOW) and disables -(registered HIGH) the command decoder. All commands are masked when CS# -is registered HIGH. CS# provides for external rank selection on systems -with multiple ranks. CS# is considered part of the command code. CS# is -referenced to VREFCA. - -*Input Data Mask Line:* DM is an input mask signal for write data. Input -data is masked when DM is sampled HIGH along with the input data during -a write access. Although the DM ball is input-only, the DM loading is -designed to match that of the DQ and DQS balls. DM is referenced to -VREFDQ. - -*On-die Termination Line:* ODT enables (registered HIGH) and disables -(registered LOW) termination resistance internal to the LPDDR4 SDRAM. -When enabled in normal operation, ODT is only applied to each of the -following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, -DQS#, and DM for the x4. The ODT input is ignored if disabled via the -LOAD MODE command. ODT is referenced to VREFCA. - -.. _power-rails-1: - -Power Rails -****************** - -The *LPDDR4* memory device and the DDR3 rails on the processor are -supplied by the**TPS65941213 and TPS65941111**. Default voltage is 1.5V but can be scaled -down to 1.35V if desired. - -.. _vref: - -VREF -*************** - -The *VREF* signal is generated from a voltage divider on the **VDDS_DDR** -rail that powers the processor DDR rail and the LPDDR4 device itself. -*Figure 33* below shows the configuration of this signal and the -connection to the LPDDR4 memory device and the processor. - -.. _figure-33,Figure 33: - -.. figure:: media/image47.jpg - :width: 400px - :align: center - :alt: Fig-33: LPDDR4 VREF Design - - Fig-33: LPDDR4 VREF Design - - - -.. _gb-emmc-memory: - -4GB eMMC Memory ------------------------------------ - -The eMMC is a communication and mass data storage device that includes a -Multi-MediaCard (MMC) interface, a NAND Flash component, and a -controller on an advanced 11-signal bus, which is compliant with the MMC -system specification. The nonvolatile eMMC draws no power to maintain -stored data, delivers high performance across a wide range of operating -temperatures, and resists shock and vibration disruption. - -One of the issues faced with SD cards is that across the different -brands and even within the same brand, performance can vary. Cards use -different controllers and different memories, all of which can have bad -locations that the controller handles. But the controllers may be -optimized for reads or writes. You never know what you will be getting. -This can lead to varying rates of performance. The eMMC card is a known -controller and when coupled with the 8bit mode, 8 bits of data instead -of 4, you get double the performance which should result in quicker boot -times. - -The following sections describe the design and device that is used on -the board to implement this interface. - -.. _emmc-device: - -eMMC Device -********************************************* - -The device used is one of two different devices: - -* Micron *MTFC4GLDEA 0M WT* -* Kingston *KE4CN2H5A-A58* - -The package is a 153 ball WFBGA device on both devices. - -.. _emmc-circuit-design: - -eMMC Circuit Design -********************************************* - -:ref:`figure-34` is the design of the eMMC circuitry. The eMMC device is -connected to the MMC1 port on the processor. MMC0 is still used for the -microSD card as is currently done on the BeagleBone Black. The size -of the eMMC supplied is now 4GB. - -The device runs at 3.3V both internally and the external I/O rails. The -VCCI is an internal voltage rail to the device. The manufacturer -recommends that a 1uF capacitor be attached to this rail, but a 2.2uF -was chosen to provide a little margin. - -Pullup resistors are used to increase the rise time on the signals to -compensate for any capacitance on the board. - -.. _figure-34,Figure 34: - -.. figure:: media/image48.png - :width: 400px - :align: center - :alt: Fig-34: eMMC Memory Design - - Fig-34: eMMC Memory Design - - - -The pins used by the eMMC1 in the boot mode are listed below in *Table 6*. - -.. _table-6,Table 6: - -.. figure:: media/image49.png - :width: 400px - :align: center - :alt: Table 6: eMMC Boot Pins - - Table 6: eMMC Boot Pins - - -For eMMC devices the ROM will only support raw mode. The ROM Code reads -out raw sectors from image or the booting file within the file system -and boots from it. In raw mode the booting image can be located at one -of the four consecutive locations in the main area: offset 0x0 / 0x20000 -(128 KB) / 0x40000 (256 KB) / 0x60000 (384 KB). For this reason, a -booting image shall not exceed 128KB in size. However it is possible to -flash a device with an image greater than 128KB starting at one of the -aforementioned locations. Therefore the ROM Code does not check the -image size. The only drawback is that the image will cross the -subsequent image boundary. The raw mode is detected by reading sectors -#0, #256, #512, #768. The content of these sectors is then verified for -presence of a TOC structure. In the case of a *GP Device*, a -Configuration Header (CH)*must* be located in the first sector followed -by a *GP header*. The CH might be void (only containing a CHSETTINGS -item for which the Valid field is zero). - -The ROM only supports the 4-bit mode. After the initial boot, the switch -can be made to 8-bit mode for increasing the overall performance of the -eMMC interface. - -.. _board-id-eeprom: - -Board ID EEPROM ------------------------------------ - -BeagleBone is equipped with a single 32Kbit(4KB) 24LC32AT-I/OT -EEPROM to allow the SW to identify the board. *Table 7* below defined -the contents of the EEPROM. - -.. _table-7,Table 7: - -.. list-table:: Table 7: EEPROM Contents - :header-rows: 1 - - * - Name - - Size (bytes) - - Contents - * - Header - - 4 - - 0xAA, 0x55, 0x33, EE - * - Board Name - - 8 - - Name for board in ASCII: A335BNLT - * - Version - - 4 - - Hardware version code for board in ASCII: 00A3 for Rev A3, 00A4 for Rev A4, 00A5 for Rev A5,00A6 for Rev A6,00B0 for Rev B, and 00C0 for Rev C. - * - Serial Number - - 12 - - Serial number of the board. This is a 12 character string which is: WWYY4P16nnnn where: WW 2 digit week of the year of production YY 2 digit year of production BBBK BeagleBone AI-64 nnnn incrementing board number - * - Configuration Option - - 32 - - Codes to show the configuration setup on this board.All FF - * - RSVD - - 6 - - FF FF FF FF FF FF - * - RSVD - - 6 - - FF FF FF FF FF FF - * - RSVD - - 6 - - FF FF FF FF FF FF - * - Available - - 4018 - - Available space for other non-volatile codes/data - -:ref:`figure-35` shows the new design on the EEPROM interface. - -.. _figure-35,Figure 35: - -.. figure:: media/image50.png - :width: 400px - :align: center - :alt: Figure 35. EEPROM Design Rev A5 - - Fig-35: EEPROM Design Rev A5 - - - -The EEPROM is accessed by the processor using the I2C 0 bus. The *WP* -pin is enabled by default. By grounding the test point, the write -protection is removed. - -The first 48 locations should not be written to if you choose to use the -extras storage space in the EEPROM for other purposes. If you do, it -could prevent the board from booting properly as the SW uses this -information to determine how to set up the board. - -.. _micro-secure-digital: - -Micro Secure Digital ------------------------------------ - -The microSD connector on the board will support a microSD card that can -be used for booting or file storage on BeagleBone AI-64. - -.. _microsd-design: - -microSD Design -********************************************* - -:ref:`figure-36` below is the design of the microSD interface on the board. - -.. _figure-36,Figure 36: - -.. figure:: media/image51.png - :width: 400px - :align: center - :alt: Figure 36. microSD Design - - Fig-36: microSD Design - - - -The signals *MMC0-3* are the data lines for the transfer of data between -the processor and the microSD connector. - -The *MMC0_CLK* signal clocks the data in and out of the microSD card. - -The *MMCO_CMD* signal indicates that a command versus data is being sent. - -There is no separate card detect pin in the microSD specification. It -uses *MMCO_DAT3* for that function. However, most microSD connectors -still supply a CD function on the connectors. In BeagleBone AI-64 -design, this pin is connected to the**MMC0_SDCD** pin for use by the -processor. You can also change the pin to *GPIO0_6*, which is able to -wake up the processor from a sleep mode when an microSD card is inserted -into the connector. - -Pullup resistors are provided on the signals to increase the rise times -of the signals to overcome PCB capacitance. - -Power is provided from the *VDD_3V3B* rail and a 10uF capacitor is -provided for filtering. - -.. _user-leds: - -User LEDs ------------------------------------ - -There are four user LEDs on BeagleBone AI-64. These are connected to -GPIO pins on the processor. *Figure 37* shows the interfaces for the -user LEDs. - -.. _figure-37,Figure 37: - -.. figure:: media/image52.png - :width: 400px - :align: center - :alt: Figure 37. User LEDs - - Fig-37: User LEDs - -Resistors R71-R74 were changed to 4.75K on the revision A5B and later -boards. - -:ref:`table-8` shows the signals used to control the four LEDs from the -processor. - -.. _table-8,Table 8: - -.. list-table:: Table 8: User LED Control Signals/Pins - :header-rows: 1 - - * - LED - - GPIO SIGNAL - - PROC PIN - * - USR0 - - GPIO1_21 - - V15 - * - USR1 - - GPIO1_22 - - U15 - * - USR2 - - GPIO1_23 - - T15 - * - USR3 - - GPIO1_24 - - V16 - - - -A logic level of “1†will cause the LEDs to turn on. - -.. _boot-configuration: - -Boot Configuration ------------------------------------ - -The design supports two groups of boot options on the board. The user -can switch between these modes via the Boot button. The primary boot -source is the onboard eMMC device. By holding the Boot button, the user -can force the board to boot from the microSD slot. This enables the eMMC -to be overwritten when needed or to just boot an alternate image. The -following sections describe how the boot configuration works. - -In most applications, including those that use the provided demo -distributions available from `beagleboard.org <http://beagleboard.org/>`_ the processor-external boot code is composed of two stages. After the -primary boot code in the processor ROM passes control, a secondary stage -(secondary program loader -- "SPL" or "MLO") takes over. The SPL stage -initializes only the required devices to continue the boot process, and -then control is transferred to the third stage "U-boot". Based on the -settings of the boot pins, the ROM knows where to go and get the SPL and -UBoot code. In the case of BeagleBone AI-64, that is either eMMC or -microSD based on the position of the boot switch. - -.. _boot-configuration-design: - -Boot Configuration Design -********************************************* - -:ref:`figure-38` shows the circuitry that is involved in the boot -configuration process. On power up, these pins are read by the processor -to determine the boot order. S2 is used to change the level of one bit -from HI to LO which changes the boot order. - -.. _figure-38,Figure 38: - -.. figure:: media/image53.png - :width: 400px - :align: center - :alt: Figure 38. Processor Boot Configuration Design - - Fig-38: Processor Boot Configuration Design - -It is possible to override these setting via the expansion headers. But -be careful not to add too much load such that it could interfere with -the operation of the display interface or LCD panels. If you choose to -override these settings, it is strongly recommended that you gate these -signals with the *SYS_RESETn* signal. This ensures that after coming out -of reset these signals are removed from the expansion pins. - -.. _default-boot-options: - -Default Boot Options ------------------------------------ - -Based on the selected option found in :ref:`figure-39` below, each of the -boot sequences for each of the two settings is shown. - -.. _figure-39,Figure 39: - -.. figure:: media/image54.jpg - :width: 400px - :align: center - :alt: Figure 39. Processor Boot Configuration - - Fig-39: Processor Boot Configuration - -The first row in :ref:`figure-39` is the default setting. On boot, the -processor will look for the eMMC on the MMC1 port first, followed by the -microSD slot on MMC0, USB0 and UART0. In the event there is no microSD -card and the eMMC is empty, UART0 or USB0 could be used as the board -source. - -If you have a microSD card from which you need to boot from, hold the -boot button down. On boot, the processor will look for the SPIO0 port -first, then microSD on the MMC0 port, followed by USB0 and UART0. In the -event there is no microSD card and the eMMC is empty, USB0 or UART0 -could be used as the board source. - -.. _ethernet: - -10/100 Ethernet ------------------------------------ - -BeagleBone AI-64 is equipped with a 10/100 Ethernet interface. It -uses the same PHY as is used on the BeagleBone Black. The design is -described in the following sections. - -.. _ethernet-processor-interface: - -Ethernet Processor Interface -********************************************* - -:ref:`figure-40` shows the connections between the processor and the PHY. The -interface is in the MII mode of operation. - -.. _figure-40,Figure 40: - -.. figure:: media/image55.png - :width: 400px - :align: center - :alt: Figure 40. Ethernet Processor Interface - - Fig-40: Ethernet Processor Interface - - - -This is the same interface as is used on BeagleBone. No changes were -made in this design for the board. - -.. _ethernet-connector-interface: - -Ethernet Connector Interface -********************************************* - -The off board side of the PHY connections are shown in *Figure 41* -below. - -.. _figure-41,Figure 41: - -.. figure:: media/image56.png - :width: 400px - :align: center - :alt: Figure 41. Ethernet Connector Interface - - Fig-41: Ethernet Connector Interface - -This is the same interface as is used on BeagleBone. No changes were -made in this design for the board. - -.. _ethernet-phy-power-reset-and-clocks: - -Ethernet PHY Power, Reset, and Clocks -********************************************* - -:ref:`figure-42` shows the power, reset, and lock connections to -the **LAN8710A** PHY. Each of these areas is discussed in more detail in -the following sections. - -.. _figure-42,Figure 42: - -.. figure:: media/image57.png - :width: 400px - :align: center - :alt: .Figure 42. Ethernet PHY, Power, Reset, and Clocks - - Fig-42: Ethernet PHY, Power, Reset, and Clocks - - - -VDD_3V3B Rail -***************** - -The VDD_3V3B rail is the main power rail for the *LAN8710A*. It -originates at the VD_3V3B regulator and is the primary rail that -supports all of the peripherals on the board. This rail also supplies -the VDDIO rails which set the voltage levels for all of the I/O signals -between the processor and the **LAN8710A**. - -VDD_PHYA Rail -******************* - -A filtered version of VDD_3V3B rail is connected to the VDD rails of the -LAN8710 and the termination resistors on the Ethernet signals. It is -labeled as *VDD_PHYA*. The filtering inductor helps block transients -that may be seen on the VDD_3V3B rail. - -PHY_VDDCR Rail -********************* - -The *PHY_VDDCR* rail originates inside the LAN8710A. Filter and bypass -capacitors are used to filter the rail. Only circuitry inside the -LAN8710A uses this rail. - -SYS_RESET -****************** - -The reset of the LAN8710A is controlled via the *SYS_RESETn* signal, the -main board reset line. - -Clock Signals -********************* - -A crystal is used to create the clock for the LAN8710A. The processor -uses the *RMII_RXCLK* signal to provide the clocking for the data -between the processor and the LAN8710A. - -.. _lan8710a-mode-pins: - -LAN8710A Mode Pins -********************* - -There are mode pins on the LAN8710A that sets the operational mode for -the PHY when coming out of reset. These signals are also used to -communicate between the processor and the LAN8710A. As a result, these -signals can be driven by the processor which can cause the PHY not to be -initialized correctly. To ensure that this does not happen, three low -value pull up resistors are used. *Figure 43* below shows the three mode -pin resistors. - -.. _figure-43,Figure 43: - -.. figure:: media/image97.png - :width: 400px - :align: center - :alt: Figure 43. Ethernet PHY Mode Pins - - Fig-43: Ethernet PHY Mode Pins - -This will set the mode to be 111, which enables all modes and enables -auto-negotiation. - -.. _hdmi-interface-1: - -Display Port Interface ------------------------------------ - -BeagleBone AI-64 has an onboard Display Port framer that converts the LCD -signals and audio signals to drive a Display Port monitor. The design uses the on chip -internal Display Port Framer. - -The following sections provide more detail into the design of this -interface. - -.. _supported-resolutions: - -Supported Resolutions -**************************** - -The maximum resolution supported by BeagleBone AI-64 is 1280x1024 @ -60Hz. *Table 9* below shows the supported resolutions. Not all -resolutions may work on all monitors, but these have been tested and -shown to work on at least one monitor. EDID is supported on the -BeagleBone AI-64. Based on the EDID reading from the connected monitor, -the highest compatible resolution is selected. - -.Table 9. HDMI Supported Monitor Adapter Resolutions -[cols"4,1",options"header",] - -.. list-table:: Table 9. HDMI Supported Monitor Adapter Resolutions - :header-rows: 1 - - * - RESOLUTION - - AUDIO - * - 800 x 600 @60Hz - - - * - 800 x 600 @56Hz - - - * - 640 x 480 @75Hz - - - * - 640 x 480 @60Hz - - YES - * - 720 x 400 @70Hz - - - * - 1280 x 1024 @75Hz - - - * - 1024 x 768 @75Hz - - - * - 1024 x 768 @70Hz - - - * - 1024 x 768 @60Hz - - - * - 800 x 600 @75Hz - - - * - 800 x 600 @72Hz - - - * - 720 x 480 @60Hz - - YES - * - 1280 x 720 @60Hz - - YES - * - 1920x1080 @24Hz - - YES - - -.. note :: - - The updated software image used on the Rev A5B and later boards added support for 1920x1080@24HZ. - - -Audio is limited to CEA supported resolutions. LCD panels only activate -the audio in CEA modes. This is a function of the specification and is -not something that can be fixed on the board via a hardware change or a -software change. - -.. _hdmi-framer: - -Display Port Framer -********************************************* - -insert processor Display Port framer doc here - -.. _hdmi-video-processor-interface: - -Display Port Video Processor Interface -********************************************* - -insert processor Display Port V-interface doc here - -.. _hdmi-control-processor-interface: - -Display Port Control Processor Interface -********************************************* - -insert processor Display Port C-interface doc here - -.. _interrupt-signal: - -Interrupt Signal -********************************************* - -insert processor Display Port interrupt doc here - -.. _audio-interface: - -Audio Interface -********************************************* - -insert processor Display Port audio doc here - -.. _power-connections: - -Power Connections -********************************************* - -guesing this doesn’t exist on this device - -.. _hdmi-connector-interface: - -miniDP Connector Interface -********************************************* - -insert processor Mini Display Port connector doc here - -.. _usb-host: - -USB Host ------------------------------------ - -The board is equipped with a single USB host interface accessible from a -single USB Type A female connector. :ref:`figure-48` is the design of the USB -Host circuitry. - -.. _figure-48,Figure 48: - -.. figure:: media/image66.png - :width: 400px - :align: center - :alt: Figure 48. USB Host circuit - - Fig-48: USB Host circuit - -.. _power-switch: - -Power Switch -********************************************* - -*U8* is a switch that allows the power to the connector to be turned on -or off by the processor. It also has an over current detection that can -alert the processor if the current gets too high via the**USB1_OC** -signal. The power is controlled by the *USB1_DRVBUS* signal from the -processor. - -.. _esd-protection: - -ESD Protection -********************************************* - -*U9* is the ESD protection for the signals that go to the connector. - -.. _filter-options: - -Filter Options -********************************************* - -*FB7* and **FB8** were added to assist in passing the FCC emissions test. -The *USB1_VBUS* signal is used by the processor to detect that the 5V is -present on the connector. *FB7* is populated and *FB8* is replaced with -a .1 ohm resistor. - -.. _pru-icss: - -PRU-ICSS ------------------------------------ - -The PRU-ICSS module is located inside the TDA4VM processor. Access to -these pins is provided by the expansion headers and is multiplexed with -other functions on the board. Access is not provided to all of the -available pins. - -All documentation is located at http://git.beagleboard.org/beagleboard/am335x_pru_package - -This feature is not supported by Texas Instruments. - -.. _pru-icss-features: - -PRU-ICSS Features -********************************************* - -The features of the PRU-ICSS include: - -Two independent programmable real-time (PRU) cores: - -* 32-Bit Load/Store RISC architecture -* 8K Byte instruction RAM (2K instructions) per core -* 8K Bytes data RAM per core -* 12K Bytes shared RAM -* Operating frequency of 200 MHz -* PRU operation is little endian similar to ARM processor -* All memories within PRU-ICSS support parity -* Includes Interrupt Controller for system event handling -* Fast I/O interface - -*16 input pins and 16 output pins per PRU core. (Not all of these are -accessible on BeagleBone AI-64).* - -.. _pru-icss-block-diagram: - -PRU-ICSS Block Diagram -***************************** - -:ref:`figure-49` is a high level block diagram of the PRU-ICSS. - -.. _figure-49,Figure 49: - -.. figure:: media/image67.png - :width: 400px - :align: center - :alt: PRU-ICSS Block Diagram - - PRU-ICSS Block Diagram - -.. _pru-icss-pin-access: - -PRU-ICSS Pin Access -********************************************* - -Both PRU 0 and PRU1 are accessible from the expansion headers. Some may -not be useable without first disabling functions on the board like LCD -for example. Listed below is what ports can be accessed on each PRU. - -* 8 outputs or 9 inputs PRU1 -* 13 outputs or 14 inputs -* UART0_TXD, UART0_RXD, UART0_CTS, UART0_RTS - -:ref:`table-11` below shows which PRU-ICSS signals can be accessed on the -BeagleBone AI-64 and on which connector and pins they are accessible -from. Some signals are accessible on the same pins. - -.. _table-11,Table 11: - -.. list-table:: Table 11: PRU0 and PRU1 Access - :header-rows: 1 - - * - - - PIN - - PROC - - NAME - - - - - - - * - P8 - - 11 - - R12 - - GPIO1_13 - - - - pr1_pru0_pru_r30_15 (Output) - - - * - - - 12 - - T12 - - GPIO1_12 - - - - pr1_pru0_pru_r30_14 (Output) - - - * - - - 15 - - U13 - - GPIO1_15 - - - - pr1_pru0_pru_r31_15 (Input) - - - * - - - 16 - - V13 - - GPIO1_14 - - - - pr1_pru0_pru_r31_14 (Input) - - - * - - - 20 - - V9 - - GPIO1_31 - - pr1_pru1_pru_r30_13 (Output) - - pr1_pru1_pru_r31_13 (INPUT) - - - * - - - 21 - - U9 - - GPIO1_30 - - pr1_pru1_pru_r30_12 (Output) - - pr1_pru1_pru_r31_12 (INPUT) - - - * - - - 27 - - U5 - - GPIO2_22 - - pr1_pru1_pru_r30_8 (Output) - - pr1_pru1_pru_r31_8 (INPUT) - - - * - - - 28 - - V5 - - GPIO2_24 - - pr1_pru1_pru_r30_10 (Output) - - pr1_pru1_pru_r31_10 (INPUT) - - - * - - - 29 - - R5 - - GPIO2_23 - - pr1_pru1_pru_r30_9 (Output) - - pr1_pru1_pru_r31_9 (INPUT) - - - * - - - 39 - - T3 - - GPIO2_12 - - pr1_pru1_pru_r30_6 (Output) - - pr1_pru1_pru_r31_6 (INPUT) - - - * - - - 40 - - T4 - - GPIO2_13 - - pr1_pru1_pru_r30_7 (Output) - - pr1_pru1_pru_r31_7 (INPUT) - - - * - - - 41 - - T1 - - GPIO2_10 - - pr1_pru1_pru_r30_4 (Output) - - pr1_pru1_pru_r31_4 (INPUT) - - - * - - - 42 - - T2 - - GPIO2_11 - - pr1_pru1_pru_r30_5 (Output) - - pr1_pru1_pru_r31_5 (INPUT) - - - * - - - 43 - - R3 - - GPIO2_8 - - pr1_pru1_pru_r30_2 (Output) - - pr1_pru1_pru_r31_2 (INPUT) - - - * - - - 44 - - R4 - - GPIO2_9 - - pr1_pru1_pru_r30_3 (Output) - - pr1_pru1_pru_r31_3 (INPUT) - - - * - - - 45 - - R1 - - GPIO2_6 - - pr1_pru1_pru_r30_0 (Output) - - pr1_pru1_pru_r31_0 (INPUT) - - - * - - - 46 - - R2 - - GPIO2_7 - - pr1_pru1_pru_r30_1 (Output) - - pr1_pru1_pru_r31_1 (INPUT) - - - * - - - - - - - - - - - - - - * - P9 - - 17 - - A16 - - I2C1_SCL - - pr1_uart0_txd - - - - - * - - - 18 - - B16 - - I2C1_SDA - - pr1_uart0_rxd - - - - - * - - - 19 - - D17 - - I2C2_SCL - - pr1_uart0_rts_n - - - - - * - - - 20 - - D18 - - I2C2_SDA - - pr1_uart0_cts_n - - - - - * - - - 21 - - B17 - - UART2_TXD - - pr1_uart0_rts_n - - - - - * - - - 22 - - A17 - - UART2_RXD - - pr1_uart0_cts_n - - - - - * - - - 24 - - D15 - - UART1_TXD - - pr1_uart0_txd - - pr1_pru0_pru_r31_16 (Input) - - - * - - - 25 - - A14 - - GPIO3_21footnote:[GPIO3_21 is also the 24.576MHZ clock input to the processor to enable HDMI audio. To use this pin the oscillator must be disabled.] - - pr1_pru0_pru_r30_5 (Output) - - pr1_pru0_pru_r31_5 (Input) - - - * - - - 26 - - D16 - - UART1_RXD - - pr1_uart0_rxd - - pr1_pru1_pru_r31_16 - - - * - - - 27 - - C13 - - GPIO3_19 - - pr1_pru0_pru_r30_7 (Output) - - pr1_pru0_pru_r31_7 (Input) - - - * - - - 28 - - C12 - - SPI1_CS0 - - eCAP2_in_PWM2_out - - pr1_pru0_pru_r30_3 (Output) - - pr1_pru0_pru_r31_3 (Input) - * - - - 29 - - B13 - - SPI1_D0 - - pr1_pru0_pru_r30_1 (Output) - - pr1_pru0_pru_r31_1 (Input) - - - * - - - 30 - - D12 - - SPI1_D1 - - pr1_pru0_pru_r30_2 (Output) - - pr1_pru0_pru_r31_2 (Input) - - - * - - - 31 - - A13 - - SPI1_SCLK - - pr1_pru0_pru_r30_0 (Output) - - pr1_pru0_pru_r31_0 (Input) - - - - diff --git a/boards/beaglebone/ai-64/ch07.rst b/boards/beaglebone/ai-64/ch07.rst deleted file mode 100644 index 699101b182ef40081e0b50924ddac34b4a858e59..0000000000000000000000000000000000000000 --- a/boards/beaglebone/ai-64/ch07.rst +++ /dev/null @@ -1,394 +0,0 @@ -:orphan: - -.. _connectors: - -Connectors -############# - -This section describes each of the connectors on the board. - -.. _section-7-1,Section 7.1 Expansion Connectors: - -Expansion Connectors ------------------------------ - -The expansion interface on the board is comprised of two 46 pin -connectors. All signals on the expansion headers are 3.3V unless -otherwise indicated. - -.. note :: - - Do not connect 5V logic level signals to these pins or the board will be damaged. - -.. note :: - - DO NOT APPLY VOLTAGE TO ANY I/O PIN WHEN POWER IS NOT SUPPLIED TO THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY. - NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS RESET LINE GOES HIGH. - -:ref:`figure-50` shows the location of the expansion connectors. - -.. _figure-50,Figure 50: - -.. figure:: media/image68.jpg - :width: 400px - :align: center - :alt: Figure 50. Expansion Connector Location - - Fig-50: Expansion Connector Location - -The location and spacing of the expansion headers are the same as on the BeagleBone Black. - -.. _connector-p8-and-p9: - -Connector P8 and P9 -************************** - -:ref:`table-12` shows the pin bindings for **P8** and **P9** expansion headers. Signals -can be connected to theese connectors based on setting the pin mux on the -processor, but this is the default settings on power up. The SW is -responsible for setting the default function of each pin. There are some -signals that have not been listed here. Refer to the processor -documentation for more information on these pins and detailed -descriptions of all of the pins listed. In some cases there may not be -enough signals to complete a group of signals that may be required to -implement a total interface. - -The *BALL NUMBER* Identifier is the pin number in the processor documentation. - -The *PIN No.* column is the pin number on the expansion header. - -The *ADDRESS* column is the pin CONFIGURATION address??? for each pin. - -The *MUXMODE[14:0] SETTINGS* are the possible pin configurations. - - -*NOTE: DO NOT APPLY VOLTAGE TO ANY I/O PIN WHEN POWER IS NOT SUPPLIED TO -THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.* - -*NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES HIGH.* - - -.. - #TODO# this is a total mess! - | *PIN No.* | *ADDRESS* | *REGISTER NAME* | *BALL NUMBER* | *MUXMODE[14:0] SETTINGS* ||||||||||||||| - | *PIN No.* | *ADDRESS* | *REGISTER NAME* | *BALL NUMBER* | *0* | *1* | *2* | *3* | *4* | *5* | *6* | *7* | *8* | *9* | *10* | *11* | *12* | *13* | *14* | *Bootstrap* | - | P8_03 | 0x00011C054 | PADCONFIG21 | AH21 | PRG1_PRU0_GPO19 | PRG1_PRU0_GPI19 | PRG1_IEP0_EDC_SYNC_OUT0 | PRG1_PWM0_TZ_OUT | | RMII5_TXD0 | MCAN6_TX | GPIO0_20 | | | VOUT0_EXTPCLKIN | VPFE0_PCLK | MCASP4_AFSX | | | - |P8_04 |0x00011C0C4 | PADCONFIG49 | AC29 | PRG0_PRU0_GPO5 | PRG0_PRU0_GPI5 | | PRG0_PWM3_B2 | | RMII3_TXD0 | | GPIO0_48 | GPMC0_AD0 | | | | MCASP0_AXR3 | | | BOOTMODE2 - |P8_05 |0x00011C088 | PADCONFIG34 | AH25 | PRG1_PRU1_GPO12 | PRG1_PRU1_GPI12 | PRG1_RGMII2_TD1 | PRG1_PWM1_A0 | RGMII2_TD1 | | MCAN7_TX | GPIO0_33 | RGMII8_TD1 | | VOUT0_DATA12 | | MCASP9_AFSX | | | - |P8_06 |0x00011C08C | PADCONFIG35 | AG25 | PRG1_PRU1_GPO13 | PRG1_PRU1_GPI13 | PRG1_RGMII2_TD2 | PRG1_PWM1_B0 | RGMII2_TD2 | | MCAN7_RX | GPIO0_34 | RGMII8_TD2 | | VOUT0_DATA13 | VPFE0_DATA8 | MCASP9_AXR0 | MCASP4_ACLKR | | - |P8_07 |0x00011C03C | PADCONFIG15 | AD24 | PRG1_PRU0_GPO14 | PRG1_PRU0_GPI14 | PRG1_RGMII1_TD3 | PRG1_PWM0_A1 | RGMII1_TD3 | | MCAN5_RX | GPIO0_15 | | RGMII7_TD3 | VOUT0_DATA19 | VPFE0_DATA3 | MCASP7_AXR1 | | | - |P8_08 |0x00011C038 | PADCONFIG14 | AG24 | PRG1_PRU0_GPO13 | PRG1_PRU0_GPI13 | PRG1_RGMII1_TD2 | PRG1_PWM0_B0 | RGMII1_TD2 | | MCAN5_TX | GPIO0_14 | | RGMII7_TD2 | VOUT0_DATA18 | VPFE0_DATA2 | MCASP7_AXR0 | | | - |P8_09 |0x00011C044 | PADCONFIG17 | AE24 | PRG1_PRU0_GPO16 | PRG1_PRU0_GPI16 | PRG1_RGMII1_TXC | PRG1_PWM0_A2 | RGMII1_TXC | | MCAN6_RX | GPIO0_17 | | RGMII7_TXC | VOUT0_DATA21 | VPFE0_DATA5 | MCASP7_AXR3 | MCASP7_AFSR | | - |P8_10 |0x00011C040 | PADCONFIG16 | AC24 | PRG1_PRU0_GPO15 | PRG1_PRU0_GPI15 | PRG1_RGMII1_TX_CTL | PRG1_PWM0_B1 | RGMII1_TX_CTL | | MCAN6_TX | GPIO0_16 | | RGMII7_TX_CTL | VOUT0_DATA20 | VPFE0_DATA4 | MCASP7_AXR2 | MCASP7_ACLKR | | - |P8_11 |0x00011C0F4 | PADCONFIG61 | AB24 | PRG0_PRU0_GPO17 | PRG0_PRU0_GPI17 | PRG0_IEP0_EDC_SYNC_OUT1 | PRG0_PWM0_B2 | PRG0_ECAP0_SYNC_OUT | | | GPIO0_60 | GPMC0_AD5 | OBSCLK1 | | | MCASP0_AXR13 | | | BOOTMODE7 - |P8_12 |0x00011C0F0 | PADCONFIG60 | AH28 | PRG0_PRU0_GPO16 | PRG0_PRU0_GPI16 | PRG0_RGMII1_TXC | PRG0_PWM0_A2 | RGMII3_TXC | | | GPIO0_59 | | | DSS_FSYNC1 | | MCASP0_AXR12 | | | - |P8_13 |0x00011C168 | PADCONFIG90 | V27 | RGMII5_TD1 | RMII7_TXD1 | I2C3_SCL | | VOUT1_DATA4 | TRC_DATA2 | EHRPWM0_B | GPIO0_89 | GPMC0_A5 | | | | MCASP11_ACLKX | | | - |P8_14 |0x00011C130 | PADCONFIG76 | AF27 | PRG0_PRU1_GPO12 | PRG0_PRU1_GPI12 | PRG0_RGMII2_TD1 | PRG0_PWM1_A0 | RGMII4_TD1 | | | GPIO0_75 | | | | | MCASP1_AXR8 | | UART8_CTSn | - |P8_15 |0x00011C0F8 | PADCONFIG62 | AB29 | PRG0_PRU0_GPO18 | PRG0_PRU0_GPI18 | PRG0_IEP0_EDC_LATCH_IN0 | PRG0_PWM0_TZ_IN | PRG0_ECAP0_IN_APWM_OUT | | | GPIO0_61 | GPMC0_AD6 | | | | MCASP0_AXR14 | | | - |P8_16 |0x00011C0FC | PADCONFIG63 | AB28 | PRG0_PRU0_GPO19 | PRG0_PRU0_GPI19 | PRG0_IEP0_EDC_SYNC_OUT0 | PRG0_PWM0_TZ_OUT | | | | GPIO0_62 | GPMC0_AD7 | | | | MCASP0_AXR15 | | | - |P8_17 |0x00011C00C | PADCONFIG3 | AF22 | PRG1_PRU0_GPO2 | PRG1_PRU0_GPI2 | PRG1_RGMII1_RD2 | PRG1_PWM2_A0 | RGMII1_RD2 | RMII1_CRS_DV | | GPIO0_3 | GPMC0_WAIT1 | RGMII7_RD2 | | | MCASP6_AXR0 | | UART1_RXD | - |P8_18 |0x00011C010 | PADCONFIG4 | AJ23 | PRG1_PRU0_GPO3 | PRG1_PRU0_GPI3 | PRG1_RGMII1_RD3 | PRG1_PWM3_A2 | RGMII1_RD3 | RMII1_RX_ER | | GPIO0_4 | GPMC0_DIR | RGMII7_RD3 | | | MCASP6_AXR1 | | UART1_TXD | - |P8_19 |0x00011C164 | PADCONFIG89 | V29 | RGMII5_TD2 | UART3_TXD | | SYNC3_OUT | VOUT1_DATA3 | TRC_DATA1 | EHRPWM0_A | GPIO0_88 | GPMC0_A4 | | | | MCASP10_AXR1 | | | - |P8_20 |0x00011C134 | PADCONFIG77 | AF26 | PRG0_PRU1_GPO13 | PRG0_PRU1_GPI13 | PRG0_RGMII2_TD2 | PRG0_PWM1_B0 | RGMII4_TD2 | | | GPIO0_76 | | | | | MCASP1_AXR9 | | UART8_RTSn | - |P8_21 |0x00011C07C | PADCONFIG31 | AF21 | PRG1_PRU1_GPO9 | PRG1_PRU1_GPI9 | PRG1_UART0_RXD | | SPI6_CS3 | RMII6_RXD1 | MCAN8_TX | GPIO0_30 | GPMC0_CSn0 | PRG1_IEP0_EDIO_DATA_IN_OUT30 | VOUT0_DATA9 | | MCASP4_AXR3 | | | - |P8_22 |0x00011C014 | PADCONFIG5 | AH23 | PRG1_PRU0_GPO4 | PRG1_PRU0_GPI4 | PRG1_RGMII1_RX_CTL | PRG1_PWM2_B0 | RGMII1_RX_CTL | RMII1_TXD0 | | GPIO0_5 | GPMC0_CSn2 | RGMII7_RX_CTL | | | MCASP6_AXR2 | MCASP6_ACLKR | UART2_RXD | - |P8_23 |0x00011C080 | PADCONFIG32 | AB23 | PRG1_PRU1_GPO10 | PRG1_PRU1_GPI10 | PRG1_UART0_TXD | PRG1_PWM2_TZ_IN | | RMII6_CRS_DV | MCAN8_RX | GPIO0_31 | GPMC0_CLKOUT | PRG1_IEP0_EDIO_DATA_IN_OUT31 | VOUT0_DATA10 | GPMC0_FCLK_MUX | MCASP5_ACLKX | | | - |P8_24 |0x00011C018 | PADCONFIG6 | AD20 | PRG1_PRU0_GPO5 | PRG1_PRU0_GPI5 | | PRG1_PWM3_B2 | | RMII1_TX_EN | | GPIO0_6 | GPMC0_WEn | | | | MCASP3_AXR0 | | | BOOTMODE0 - |P8_25 |0x00011C090 | PADCONFIG36 | AH26 | PRG1_PRU1_GPO14 | PRG1_PRU1_GPI14 | PRG1_RGMII2_TD3 | PRG1_PWM1_A1 | RGMII2_TD3 | | MCAN8_TX | GPIO0_35 | RGMII8_TD3 | | VOUT0_DATA14 | | MCASP9_AXR1 | MCASP4_AFSR | | - |P8_26 |0x00011C0D0 | PADCONFIG52 | AC27 | PRG0_PRU0_GPO8 | PRG0_PRU0_GPI8 | | PRG0_PWM2_A1 | | | MCAN9_RX | GPIO0_51 | GPMC0_AD2 | | | | MCASP0_AXR6 | | UART6_RXD | - |P8_27 |0x00011C120 | PADCONFIG72 | AA28 | PRG0_PRU1_GPO8 | PRG0_PRU1_GPI8 | | PRG0_PWM2_TZ_OUT | | | MCAN11_RX | GPIO0_71 | GPMC0_AD10 | | | | MCASP1_AFSX | | | - |P8_28 |0x00011C124 | PADCONFIG73 | Y24 | PRG0_PRU1_GPO9 | PRG0_PRU1_GPI9 | PRG0_UART0_RXD | | SPI3_CS3 | | PRG0_IEP0_EDIO_DATA_IN_OUT30 | GPIO0_72 | GPMC0_AD11 | | DSS_FSYNC3 | | MCASP1_AXR5 | | UART8_RXD | - |P8_29 |0x00011C128 | PADCONFIG74 | AA25 | PRG0_PRU1_GPO10 | PRG0_PRU1_GPI10 | PRG0_UART0_TXD | PRG0_PWM2_TZ_IN | | | PRG0_IEP0_EDIO_DATA_IN_OUT31 | GPIO0_73 | GPMC0_AD12 | CLKOUT | | | MCASP1_AXR6 | | UART8_TXD | - |P8_30 |0x00011C12C | PADCONFIG75 | AG26 | PRG0_PRU1_GPO11 | PRG0_PRU1_GPI11 | PRG0_RGMII2_TD0 | | RGMII4_TD0 | RMII4_TX_EN | | GPIO0_74 | GPMC0_A26 | | | | MCASP1_AXR7 | | | - |P8_31A |0x00011C084 | PADCONFIG33 | AJ25 | PRG1_PRU1_GPO11 | PRG1_PRU1_GPI11 | PRG1_RGMII2_TD0 | | RGMII2_TD0 | RMII2_TX_EN | | GPIO0_32 | RGMII8_TD0 | EQEP1_I | VOUT0_DATA11 | | MCASP9_ACLKX | | | - |P8_31B |0x00011C100 | PADCONFIG64 | AE29 | PRG0_PRU1_GPO0 | PRG0_PRU1_GPI0 | PRG0_RGMII2_RD0 | | RGMII4_RD0 | RMII4_RXD0 | | GPIO0_63 | UART4_CTSn | | | | MCASP1_AXR0 | | UART5_RXD | - |P8_32A |0x00011C06C | PADCONFIG27 | AG21 | PRG1_PRU1_GPO5 | PRG1_PRU1_GPI5 | | | | RMII5_TX_EN | MCAN6_RX | GPIO0_26 | GPMC0_WPn | EQEP1_S | VOUT0_DATA5 | | MCASP4_AXR0 | | TIMER_IO4 | - |P8_32B |0x00011C104 | PADCONFIG65 | AD28 | PRG0_PRU1_GPO1 | PRG0_PRU1_GPI1 | PRG0_RGMII2_RD1 | | RGMII4_RD1 | RMII4_RXD1 | | GPIO0_64 | UART4_RTSn | | | | MCASP1_AXR1 | | UART5_TXD | - |P8_33A |0x00011C068 | PADCONFIG26 | AH24 | PRG1_PRU1_GPO4 | PRG1_PRU1_GPI4 | PRG1_RGMII2_RX_CTL | PRG1_PWM2_B2 | RGMII2_RX_CTL | RMII2_TXD0 | | GPIO0_25 | RGMII8_RX_CTL | EQEP1_B | VOUT0_DATA4 | VPFE0_DATA13 | MCASP8_AXR2 | MCASP8_ACLKR | TIMER_IO3 | - |P8_33B |0x00011C1C0 | PADCONFIG112 | AA2 | SPI0_CS0 | UART0_RTSn | | | | | | GPIO0_111 | | | | | | | | - |P8_34 |0x00011C01C | PADCONFIG7 | AD22 | PRG1_PRU0_GPO6 | PRG1_PRU0_GPI6 | PRG1_RGMII1_RXC | PRG1_PWM3_A1 | RGMII1_RXC | RMII1_TXD1 | AUDIO_EXT_REFCLK0 | GPIO0_7 | GPMC0_CSn3 | RGMII7_RXC | | | MCASP6_AXR3 | MCASP6_AFSR | UART2_TXD | - |P8_35A |0x00011C064 | PADCONFIG25 | AD23 | PRG1_PRU1_GPO3 | PRG1_PRU1_GPI3 | PRG1_RGMII2_RD3 | | RGMII2_RD3 | RMII2_RX_ER | | GPIO0_24 | RGMII8_RD3 | EQEP1_A | VOUT0_DATA3 | VPFE0_WEN | MCASP8_AXR1 | MCASP3_AFSR | TIMER_IO2 | - |P8_35B |0x00011C1D4 | PADCONFIG117 | Y3 | SPI1_CS0 | UART0_CTSn | | UART5_RXD | | | PRG0_IEP0_EDIO_OUTVALID | GPIO0_116 | PRG0_IEP0_EDC_LATCH_IN0 | | | | | | | - |P8_36 |0x00011C020 | PADCONFIG8 | AE20 | PRG1_PRU0_GPO7 | PRG1_PRU0_GPI7 | PRG1_IEP0_EDC_LATCH_IN1 | PRG1_PWM3_B1 | | AUDIO_EXT_REFCLK1 | MCAN4_TX | GPIO0_8 | | | | | MCASP3_AXR1 | | | - |P8_37A |0x00011C1AC | PADCONFIG107 | Y27 | RGMII6_RD2 | UART4_RTSn | | UART5_TXD | | TRC_DATA19 | EHRPWM5_A | GPIO0_106 | GPMC0_A22 | | | | MCASP11_AXR5 | | | - |P8_37B |0x00011C02C | PADCONFIG11 | AD21 | PRG1_PRU0_GPO10 | PRG1_PRU0_GPI10 | PRG1_UART0_RTSn | PRG1_PWM2_B1 | SPI6_CS2 | RMII5_CRS_DV | | GPIO0_11 | GPMC0_BE0n_CLE | PRG1_IEP0_EDIO_DATA_IN_OUT29 | OBSCLK2 | | MCASP3_AFSX | | | - |P8_38A |0x00011C1A8 | PADCONFIG106 | Y29 | RGMII6_RD3 | UART4_CTSn | | UART5_RXD | CLKOUT | TRC_DATA18 | EHRPWM_TZn_IN4 | GPIO0_105 | GPMC0_A21 | | | | MCASP11_AXR4 | | | - |P8_38B |0x00011C024 | PADCONFIG9 | AJ20 | PRG1_PRU0_GPO8 | PRG1_PRU0_GPI8 | | PRG1_PWM2_A1 | | RMII5_RXD0 | MCAN4_RX | GPIO0_9 | GPMC0_OEn_REn | | VOUT0_DATA22 | | MCASP3_AXR2 | | | - |P8_39 |0x00011C118 | PADCONFIG70 | AC26 | PRG0_PRU1_GPO6 | PRG0_PRU1_GPI6 | PRG0_RGMII2_RXC | | RGMII4_RXC | RMII4_TXD0 | | GPIO0_69 | GPMC0_A25 | | | | MCASP1_AXR3 | | | - |P8_40 |0x00011C11C | PADCONFIG71 | AA24 | PRG0_PRU1_GPO7 | PRG0_PRU1_GPI7 | PRG0_IEP1_EDC_LATCH_IN1 | | SPI3_CS0 | | MCAN11_TX | GPIO0_70 | GPMC0_AD9 | | | | MCASP1_AXR4 | | UART2_TXD | - |P8_41 |0x00011C110 | PADCONFIG68 | AD29 | PRG0_PRU1_GPO4 | PRG0_PRU1_GPI4 | PRG0_RGMII2_RX_CTL | PRG0_PWM2_B2 | RGMII4_RX_CTL | RMII4_TXD1 | | GPIO0_67 | GPMC0_A24 | | | | MCASP1_AXR2 | | | - |P8_42 |0x00011C114 | PADCONFIG69 | AB27 | PRG0_PRU1_GPO5 | PRG0_PRU1_GPI5 | | | | | | GPIO0_68 | GPMC0_AD8 | | | | MCASP1_ACLKX | | | BOOTMODE6 - |P8_43 |0x00011C108 | PADCONFIG66 | AD27 | PRG0_PRU1_GPO2 | PRG0_PRU1_GPI2 | PRG0_RGMII2_RD2 | PRG0_PWM2_A2 | RGMII4_RD2 | RMII4_CRS_DV | | GPIO0_65 | GPMC0_A23 | | | | MCASP1_ACLKR | MCASP1_AXR10 | | - |P8_44 |0x00011C10C | PADCONFIG67 | AC25 | PRG0_PRU1_GPO3 | PRG0_PRU1_GPI3 | PRG0_RGMII2_RD3 | | RGMII4_RD3 | RMII4_RX_ER | | GPIO0_66 | | | | | MCASP1_AFSR | MCASP1_AXR11 | | - |P8_45 |0x00011C140 | PADCONFIG80 | AG29 | PRG0_PRU1_GPO16 | PRG0_PRU1_GPI16 | PRG0_RGMII2_TXC | PRG0_PWM1_A2 | RGMII4_TXC | | | GPIO0_79 | | | | | MCASP2_AXR2 | | | - |P8_46 |0x00011C144 | PADCONFIG81 | Y25 | PRG0_PRU1_GPO17 | PRG0_PRU1_GPI17 | PRG0_IEP1_EDC_SYNC_OUT1 | PRG0_PWM1_B2 | SPI3_CLK | | | GPIO0_80 | GPMC0_AD13 | | | | MCASP2_AXR3 | | | BOOTMODE3 - |P9_11 |0x00011C004 | PADCONFIG1 | AC23 | PRG1_PRU0_GPO0 | PRG1_PRU0_GPI0 | PRG1_RGMII1_RD0 | PRG1_PWM3_A0 | RGMII1_RD0 | RMII1_RXD0 | | GPIO0_1 | GPMC0_BE1n | RGMII7_RD0 | | | MCASP6_ACLKX | | UART0_RXD | - |P9_12 |0x00011C0B8 | PADCONFIG46 | AE27 | PRG0_PRU0_GPO2 | PRG0_PRU0_GPI2 | PRG0_RGMII1_RD2 | PRG0_PWM2_A0 | RGMII3_RD2 | RMII3_CRS_DV | | GPIO0_45 | UART3_RXD | | | | MCASP0_ACLKR | | | - |P9_13 |0x00011C008 | PADCONFIG2 | AG22 | PRG1_PRU0_GPO1 | PRG1_PRU0_GPI1 | PRG1_RGMII1_RD1 | PRG1_PWM3_B0 | RGMII1_RD1 | RMII1_RXD1 | | GPIO0_2 | GPMC0_WAIT0 | RGMII7_RD1 | | | MCASP6_AFSX | | UART0_TXD | - |P9_14 |0x00011C178 | PADCONFIG94 | U27 | RGMII5_RD3 | UART3_CTSn | | UART6_RXD | VOUT1_DATA8 | TRC_DATA6 | EHRPWM2_A | GPIO0_93 | GPMC0_A9 | | | | MCASP11_AXR0 | | | - |P9_15 |0x00011C0C0 | PADCONFIG48 | AD25 | PRG0_PRU0_GPO4 | PRG0_PRU0_GPI4 | PRG0_RGMII1_RX_CTL | PRG0_PWM2_B0 | RGMII3_RX_CTL | RMII3_TXD1 | | GPIO0_47 | | | | | MCASP0_AXR2 | | | - |P9_16A |0x00011C17C | PADCONFIG95 | U24 | RGMII5_RD2 | UART3_RTSn | | UART6_TXD | VOUT1_DATA9 | TRC_DATA7 | EHRPWM2_B | GPIO0_94 | GPMC0_A10 | | | | MCASP11_AXR1 | | | - |P9_16B |0x00011C1DC | PADCONFIG119 | Y1 | SPI1_CLK | UART5_CTSn | I2C4_SDA | UART2_RXD | | | | GPIO0_118 | PRG0_IEP0_EDC_SYNC_OUT0 | | | | | | | - |P9_17A |0x00011C074 | PADCONFIG29 | AC21 | PRG1_PRU1_GPO7 | PRG1_PRU1_GPI7 | PRG1_IEP1_EDC_LATCH_IN1 | | SPI6_CS0 | RMII6_RX_ER | MCAN7_TX | GPIO0_28 | | | VOUT0_DATA7 | VPFE0_DATA15 | MCASP4_AXR1 | | UART3_TXD | - |P9_17B |0x00011C1D0 | PADCONFIG116 | AA3 | SPI0_D1 | | I2C6_SCL | | | | | GPIO0_115 | | | | | | | | - |P9_18A |0x00011C0A4 | PADCONFIG41 | AH22 | PRG1_PRU1_GPO19 | PRG1_PRU1_GPI19 | PRG1_IEP1_EDC_SYNC_OUT0 | PRG1_PWM1_TZ_OUT | SPI6_D1 | RMII6_TXD1 | PRG1_ECAP0_IN_APWM_OUT | GPIO0_40 | | | VOUT0_PCLK | | MCASP5_AXR1 | | | - |P9_18B |0x00011C1E4 | PADCONFIG121 | Y2 | SPI1_D1 | | I2C6_SDA | | | | | GPIO0_120 | PRG0_IEP1_EDC_SYNC_OUT0 | | | | | | | - |P9_19A |0x00011C208 | PADCONFIG130 | W5 | MCAN0_RX | | | | I2C2_SCL | | | GPIO1_1 | | | | | | | | - |P9_19B |0x00011C13C | PADCONFIG79 | AF29 | PRG0_PRU1_GPO15 | PRG0_PRU1_GPI15 | PRG0_RGMII2_TX_CTL | PRG0_PWM1_B1 | RGMII4_TX_CTL | | | GPIO0_78 | | | | | MCASP2_AXR1 | | UART2_RTSn | - |P9_20A |0x00011C20C | PADCONFIG131 | W6 | MCAN0_TX | | | | I2C2_SDA | | | GPIO1_2 | | | | | | | | - |P9_21A |0x00011C0A0 | PADCONFIG40 | AJ22 | PRG1_PRU1_GPO18 | PRG1_PRU1_GPI18 | PRG1_IEP1_EDC_LATCH_IN0 | PRG1_PWM1_TZ_IN | SPI6_D0 | RMII6_TXD0 | PRG1_ECAP0_SYNC_IN | GPIO0_39 | | VOUT0_VP2_VSYNC | VOUT0_VSYNC | | MCASP5_AXR0 | | VOUT0_VP0_VSYNC | - |P9_22A |0x00011C09C | PADCONFIG39 | AC22 | PRG1_PRU1_GPO17 | PRG1_PRU1_GPI17 | PRG1_IEP1_EDC_SYNC_OUT1 | PRG1_PWM1_B2 | SPI6_CLK | RMII6_TX_EN | PRG1_ECAP0_SYNC_OUT | GPIO0_38 | | VOUT0_VP2_DE | VOUT0_DE | VPFE0_DATA10 | MCASP5_AFSX | | VOUT0_VP0_DE | BOOTMODE1 - |P9_22B |0x00011C170 | PADCONFIG92 | U29 | RGMII5_TXC | RMII7_TX_EN | I2C6_SCL | | VOUT1_DATA6 | TRC_DATA4 | EHRPWM1_B | GPIO0_91 | GPMC0_A7 | | | | MCASP10_AXR2 | | | - |P9_23 |0x00011C028 | PADCONFIG10 | AG20 | PRG1_PRU0_GPO9 | PRG1_PRU0_GPI9 | PRG1_UART0_CTSn | PRG1_PWM3_TZ_IN | SPI6_CS1 | RMII5_RXD1 | | GPIO0_10 | GPMC0_ADVn_ALE | PRG1_IEP0_EDIO_DATA_IN_OUT28 | VOUT0_DATA23 | | MCASP3_ACLKX | | | - |P9_24A |0x00011C034 | PADCONFIG13 | AJ24 | PRG1_PRU0_GPO12 | PRG1_PRU0_GPI12 | PRG1_RGMII1_TD1 | PRG1_PWM0_A0 | RGMII1_TD1 | | MCAN4_RX | GPIO0_13 | | RGMII7_TD1 | VOUT0_DATA17 | VPFE0_DATA1 | MCASP7_AFSX | | | - |P9_24B |0x00011C1E0 | PADCONFIG120 | Y5 | SPI1_D0 | UART5_RTSn | I2C4_SCL | UART2_TXD | | | | GPIO0_119 | PRG0_IEP1_EDC_LATCH_IN0 | | | | | | | - |P9_25A |0x00011C200 | PADCONFIG128 | AC4 | UART1_CTSn | MCAN3_RX | | | SPI2_D0 | EQEP0_S | | GPIO0_127 | | | | | | | | - |P9_25B |0x00011C1A4 | PADCONFIG105 | W26 | RGMII6_RXC | | | AUDIO_EXT_REFCLK2 | VOUT1_DE | TRC_DATA17 | EHRPWM4_B | GPIO0_104 | GPMC0_A20 | VOUT1_VP0_DE | | | MCASP10_AXR7 | | | - |P9_26A |0x00011C030 | PADCONFIG12 | AF24 | PRG1_PRU0_GPO11 | PRG1_PRU0_GPI11 | PRG1_RGMII1_TD0 | PRG1_PWM3_TZ_OUT | RGMII1_TD0 | | MCAN4_TX | GPIO0_12 | | RGMII7_TD0 | VOUT0_DATA16 | VPFE0_DATA0 | MCASP7_ACLKX | | | - |P9_27A |0x00011C0BC | PADCONFIG47 | AD26 | PRG0_PRU0_GPO3 | PRG0_PRU0_GPI3 | PRG0_RGMII1_RD3 | PRG0_PWM3_A2 | RGMII3_RD3 | RMII3_RX_ER | | GPIO0_46 | UART3_TXD | | | | MCASP0_AFSR | | | - |P9_27B |0x00011C1F4 | PADCONFIG125 | AB1 | UART0_RTSn | TIMER_IO7 | SPI0_CS3 | MCAN2_TX | SPI2_CLK | EQEP0_B | | GPIO0_124 | | | | | | | | - |P9_28A |0x00011C230 | PADCONFIG140 | U2 | ECAP0_IN_APWM_OUT | SYNC0_OUT | CPTS0_RFT_CLK | | SPI2_CS3 | I3C0_SDAPULLEN | SPI7_CS0 | GPIO1_11 | | | | | | | | - |P9_28B |0x00011C0B0 | PADCONFIG44 | AF28 | PRG0_PRU0_GPO0 | PRG0_PRU0_GPI0 | PRG0_RGMII1_RD0 | PRG0_PWM3_A0 | RGMII3_RD0 | RMII3_RXD1 | | GPIO0_43 | | | | | MCASP0_AXR0 | | | - |P9_29A |0x00011C0D8 | PADCONFIG54 | AB25 | PRG0_PRU0_GPO10 | PRG0_PRU0_GPI10 | PRG0_UART0_RTSn | PRG0_PWM2_B1 | SPI3_CS2 | PRG0_IEP0_EDIO_DATA_IN_OUT29 | MCAN10_RX | GPIO0_53 | GPMC0_AD4 | | | | MCASP0_AFSX | | | - |P9_29B |0x00011C23C | PADCONFIG143 | V5 | TIMER_IO1 | ECAP2_IN_APWM_OUT | OBSCLK0 | | | | SPI7_D1 | GPIO1_14 | | | | | | | | BOOTMODE5 - |P9_30A |0x00011C0B4 | PADCONFIG45 | AE28 | PRG0_PRU0_GPO1 | PRG0_PRU0_GPI1 | PRG0_RGMII1_RD1 | PRG0_PWM3_B0 | RGMII3_RD1 | RMII3_RXD0 | | GPIO0_44 | | | | | MCASP0_AXR1 | | | - |P9_30B |0x00011C238 | PADCONFIG142 | V6 | TIMER_IO0 | ECAP1_IN_APWM_OUT | SYSCLKOUT0 | | | | SPI7_D0 | GPIO1_13 | | | | | | | | BOOTMODE4 - |P9_31A |0x00011C0D4 | PADCONFIG53 | AB26 | PRG0_PRU0_GPO9 | PRG0_PRU0_GPI9 | PRG0_UART0_CTSn | PRG0_PWM3_TZ_IN | SPI3_CS1 | PRG0_IEP0_EDIO_DATA_IN_OUT28 | MCAN10_TX | GPIO0_52 | GPMC0_AD3 | | | | MCASP0_ACLKX | | UART6_TXD | - |P9_31B |0x00011C234 | PADCONFIG141 | U3 | EXT_REFCLK1 | SYNC1_OUT | | | | | SPI7_CLK | GPIO1_12 | | | | | | | | - |P9_33A |0x00011C0CC | PADCONFIG51 | AC28 | PRG0_PRU0_GPO7 | PRG0_PRU0_GPI7 | PRG0_IEP0_EDC_LATCH_IN1 | PRG0_PWM3_B1 | PRG0_ECAP0_SYNC_IN | | MCAN9_TX | GPIO0_50 | GPMC0_AD1 | | | | MCASP0_AXR5 | | | - |P9_33B |0x04301C140 | WKUP_PADCONFIG80 | K24 | MCU_ADC0_AIN4 | | | | | | | | | | | | | | | - |P9_35A |0x00011C0E0 | PADCONFIG56 | AH27 | PRG0_PRU0_GPO12 | PRG0_PRU0_GPI12 | PRG0_RGMII1_TD1 | PRG0_PWM0_A0 | RGMII3_TD1 | | | GPIO0_55 | | | DSS_FSYNC0 | | MCASP0_AXR8 | | | - |P9_35B |0x04301C148 | WKUP_PADCONFIG82 | K29 | MCU_ADC0_AIN6 | | | | | | | | | | | | | | | - |P9_36A |0x00011C0E4 | PADCONFIG57 | AH29 | PRG0_PRU0_GPO13 | PRG0_PRU0_GPI13 | PRG0_RGMII1_TD2 | PRG0_PWM0_B0 | RGMII3_TD2 | | | GPIO0_56 | | | DSS_FSYNC2 | | MCASP0_AXR9 | | | - |P9_36B |0x04301C144 | WKUP_PADCONFIG81 | K27 | MCU_ADC0_AIN5 | | | | | | | | | | | | | | | - |P9_37A |0x00011C0E8 | PADCONFIG58 | AG28 | PRG0_PRU0_GPO14 | PRG0_PRU0_GPI14 | PRG0_RGMII1_TD3 | PRG0_PWM0_A1 | RGMII3_TD3 | | | GPIO0_57 | UART4_RXD | | | | MCASP0_AXR10 | | | - |P9_37B |0x04301C138 | WKUP_PADCONFIG78 | K28 | MCU_ADC0_AIN2 | | | | | | | | | | | | | | | - |P9_38A |0x00011C0EC | PADCONFIG59 | AG27 | PRG0_PRU0_GPO15 | PRG0_PRU0_GPI15 | PRG0_RGMII1_TX_CTL | PRG0_PWM0_B1 | RGMII3_TX_CTL | | | GPIO0_58 | UART4_TXD | | DSS_FSYNC3 | | MCASP0_AXR11 | | | - |P9_38B |0x04301C13C | WKUP_PADCONFIG79 | L28 | MCU_ADC0_AIN3 | | | | | | | | | | | | | | | - |P9_39A |0x04301C130 | WKUP_PADCONFIG76 | K25 | MCU_ADC0_AIN0 | | | | | | | | | | | | | | | - |P9_39B |0x00011C0DC | PADCONFIG55 | AJ28 | PRG0_PRU0_GPO11 | PRG0_PRU0_GPI11 | PRG0_RGMII1_TD0 | PRG0_PWM3_TZ_OUT | RGMII3_TD0 | | | GPIO0_54 | | CLKOUT | | | MCASP0_AXR7 | | | - |P9_40A |0x00011C148 | PADCONFIG82 | AA26 | PRG0_PRU1_GPO18 | PRG0_PRU1_GPI18 | PRG0_IEP1_EDC_LATCH_IN0 | PRG0_PWM1_TZ_IN | SPI3_D0 | | MCAN12_TX | GPIO0_81 | GPMC0_AD14 | | | | MCASP2_AFSX | | UART2_RXD | - |P9_40B |0x04301C134 | WKUP_PADCONFIG77 | K26 | MCU_ADC0_AIN1 | | | | | | | | | | | | | | | - |P9_41 |0x00011C204 | PADCONFIG129 | AD5 | UART1_RTSn | MCAN3_TX | | | SPI2_D1 | EQEP0_I | | GPIO1_0 | | | | | | | | - |P9_42A |0x00011C1F0 | PADCONFIG124 | AC2 | UART0_CTSn | TIMER_IO6 | SPI0_CS2 | MCAN2_RX | SPI2_CS0 | EQEP0_A | | GPIO0_123 | | | | | | | | - |P9_42B |0x00011C04C | PADCONFIG19 | AJ21 | PRG1_PRU0_GPO17 | PRG1_PRU0_GPI17 | PRG1_IEP0_EDC_SYNC_OUT1 | PRG1_PWM0_B2 | | RMII5_TXD1 | MCAN5_TX | GPIO0_18 | | | | VPFE0_DATA6 | MCASP3_AXR3 | | | | - - -.. _power-jack: - -Power Jack ----------------------------- - -The DC power jack is located next to the RJ45 Ethernet connector as -shown in :ref:`figure-51`. This uses the same power connector as is used on -the BeagleBone Black. The connector has a 2.1mm diameter center post -(5VDC) and a 5.5mm diameter outer dimension on the barrel (GND). - -.. _figure-51,Figure 51: - -.. figure:: media/image69.jpg - :width: 400px - :align: center - :alt: Figure 51. 5VDC Power Jack - - Fig-51: 5VDC Power Jack - -The board requires a regulated 5VDC +/-.25V supply at 1A. A higher -current rating may be needed if capes are plugged into the expansion -headers. Using a higher current power supply will not damage the board. - -.. _usb-client: - -USB Client ----------------------------- - -The USB Client connector is accessible on the bottom side of the board -under the row of four LEDs as shown in :ref:`figure-52`. It uses a 5 pin -miniUSB cable, the same as is used on the BeagleBone Black. The cable -is provided with the board. The cable can also be used to power the -board. - -.. _figure-52,Figure 52: - -.. figure:: media/image71.jpg - :width: 400px - :align: center - :alt: Figure 52. USB Client - - Fig-52: USB Client - -This port is a USB Client only interface and is intended for connection -to a PC. - -.. _usb-host-1: - -USB Host ----------------------------- - -There is a single USB Host connector on the board and is shown in -*Figure 53* below. - -.. figure:: media/image71.jpg - :width: 400px - :align: center - :alt: Figure 53. USB Host Connector - - Fig-53: USB Host Connector - -.. _figure-53.-usb-host-connector: - - - -The port is USB 2.0 HS compatible and can supply up to 500mA of current. -If more current or ports is needed, then a HUB can be used. - -.. _serial-header: - -Serial Header ----------------------------- - -Each board has a debug serial interface that can be accessed by using a -special serial cable that is plugged into the serial header as shown in -*Figure 54* below. - -.. figure:: media/image71.jpg - :width: 400px - :align: center - :alt: Figure 54. Serial Debug Header - - Figure 54. Serial Debug Header - -.. _figure-54.-serial-debug-header: - -Two signals are provided, TX and RX on this connector. The levels on -these signals are 3.3V. In order to access these signals, a FTDI USB to -Serial cable is recommended as shown in *Figure 55* below. - -.. figure:: media/image73.jpg - :width: 400px - :align: center - :alt: Figure-55 - -The cable can be purchased from several different places and must be the -3.3V version TTL-232R-3V3. Information on the cable itself can be found -direct from FTDI at: `http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL232R_CABLES.pdf <http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232R_CABLES.pdf>`_ - -Pin 1 of the cable is the ai-64 wire. That must align with the pin 1 on -the board which is designated by the white dot next to the connector on -the board. - -Refer to the support WIKI `http://elinux.org/BeagleBoneBlack <http://elinux.org/BeagleBoneBlack>`_ for more sources of this cable and other options that will work. - -Table is the pinout of the connector as reflected in the schematic. It -is the same as the FTDI cable which can be found at `http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232R_CABLES.pdf <http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232R_CABLES.pdf>`_ with the exception that only three pins are used on the board. The pin numbers are defined in *Table 14*. The signals are from the perspective of the board. - -.. _table-14.-j1-serial-header-pins: - -.. list-table:: Table 14: J1 Serial Header Pins - :header-rows: 1 - - * - PIN NUMBER - - SIGNAL - * - *1* - - Ground - * - *4* - - Receive - * - *5* - - Transmit - -*Figure 56* shows the pin location on the board. - -.. figure:: media/image75.jpg - :width: 400px - :align: center - :alt: Fig-56 Serial Header - - Fig-56: Serial Header - -.. _hdmi: - -HDMI ----------------------------- - -Access to the HDMI interface is through the HDMI connector that is -located on the bottom side of the board as shown in *Figure 57* below. - -.. figure:: media/image71.jpg - :width: 400px - :align: center - :alt: Figure 57. HDMI Connector - - Fig-5: HDMI Connector - -.. _figure-57.-hdmi-connector: - -The connector is microHDMI connector. This was done due to the space -limitations we had in finding a place to fit the connector. It requires -a microHDMI to HDMI cable as shown in *Figure 58* below. The cable can -be purchased from several different sources. - -.. figure:: media/image77.jpg - :width: 400px - :align: center - :alt: Figure 58. HDMI Cable - - Figure 58. HDMI Cable - -.. _microsd: - -microSD ----------------------------- - -A microSD connector is located on the back or bottom side of the board -as shown in *Figure 59* below. The microSD card is not supplied with the -board. - -.. figure:: media/image71.jpg - :width: 400px - :align: center - :alt: Figure 59. microSD Connector - - Figure 59. microSD Connector - -.. _figure-59.-microsd-connector: - -When plugging in the SD card, the writing on the card should be up. -Align the card with the connector and push to insert. Then release. -There should be a click and the card will start to eject slightly, but -it then should latch into the connector. To eject the card, push the SD -card in and then remove your finger. The SD card will be ejected from -the connector. - -Do not pull the SD card out or you could damage the connector. - -.. _ethernet-1: - -Ethernet ----------------------------- - -The board comes with a single 10/100 Ethernet interface located next to -the power jack as shown in *Figure 60*. - -.. figure:: media/image71.jpg - :width: 400px - :align: center - :alt: Figure 60. Ethernet Connector - - Figure 60. Ethernet Connector - -The PHY supports AutoMDX which means either a straight or a swap cable -can be used - -.. _jtag-connector: - -JTAG Connector ----------------------------- - -A place for an optional 20 pin CTI JTAG header is provided on the board -to facilitate the SW development and debugging of the board by using -various JTAG emulators. This header is not supplied standard on the -board. To use this, a connector will need to be soldered onto the board. - -If you need the JTAG connector you can solder it on yourself. No other -components are needed. The connector is made by Samtec and the part -number is FTR-110-03-G-D-06. You can purchase it from `www.digikey.com <http://www.digikey.com/>`_