mmc: sdhci_am654: Update phy configuration for AM65x SR2.0

The clock > CLOCK_TOO_SLOW_HZ was added to prevent the DLL
from getting enabled in the early stages of enumeration. From the
latest updates to the internal RIOT, the am654x SR2.0 IP requires
that TXCLKDLY and OTAPDLY be enabled when the DLL is not enabled.

Therefore, move the clock too slow condition to gate just the DLL properties,
enable TXCLKDLY and always have OTAPDLY enabled.

Also add a write to clkbufsel as indicated in the RIOT.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>