This adds a UIO driver the ivshmem device, found in QEMU and the
Jailhouse hypervisor. It exposes the MMIO register region and all shared
memory section to userspace. Interrupts are configured in one-shot mode
so that userspace needs to re-enable them after each event via the
Interrupt Control register. The driver registers all possible MSI-X
vectors, coalescing them into the single notifier UIO provides.

Note: Specification work for the interface is ongoing, so details may
still change.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>

Common defines and structures for the ivshmem device.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>

This allows to tag memory regions read-only, denying userspace to map
them writable. Default remains read/write.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>

commit 6b28fb6f

 upstream.

Implement .apply callback and drop the legacy callbacks(enable, disable,
config, set_polarity). In .apply() check for the current hardware status
before changing the PWM configuration.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

commit e793eef8

 upstream.

Only the Timer control register(TCLR) cannot be updated when the timer
is running. Registers like Counter register (TCRR), loader register
(TLDR) and match register (TMAR) can be updated while the counter is
running. Since TCLR is not updated in pwm_omap_dmtimer_config(), do not
stop the timer for period/duty_cycle update.

Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

commit 867beb60

 upstream.

To configure DM timer in PWM mode the following needs to be set in
OMAP_TIMER_CTRL_REG using set_pwm callback:
- Set toggle mode on PORTIMERPWM output pin
- Set trigger on overflow and match on PORTIMERPWM output pin.
- Set auto reload

This is a one time configuration and needs to be set before the start of
the DM timer. But the current driver tries to set the same configuration
for every period/duty cycle update, which is not needed. So move the PWM
setup before enabling timer and do not update it in
pwm_omap_dmtimer_config().

Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

commit 348fb6f7

 upstream.

Update the description with a brief about how PWM is generated using
OMAP DM timer and add limitations for the PWM generations. Also add a
link to the reference manual.

Suggested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

commit 54091b5f

 upstream.

pwm_omap_dmtimer.h is used only:
- to typedef struct omap_dm_timer to pwm_omap_dmtimer
- for macro PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE
Rest of the file is pretty mush unsed. So reuse omap_dm_timer
and OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE in pwm-omap-dmtimer.c
and delete the header file.

Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>

commit e6d05acd upstream.

When building arm allyesconfig:

drivers/remoteproc/omap_remoteproc.c:174:44: error: too many arguments
to function call, expected 2, have 3
        timer->timer_ops->set_load(timer->odt, 0, 0);
        ~~~~~~~~~~~~~~~~~~~~~~~~~~                ^
1 error generated.

This is due to commit 02e6d546 ("clocksource/drivers/timer-ti-dm:
Enable autoreload in set_pwm") in the clockevents tree interacting with
commit e28edc57 ("remoteproc/omap: Request a timer(s) for remoteproc
usage") from the rpmsg tree.

This should have been fixed during the merge of the remoteproc tree
since it happened after the clockevents tree merge; however, it does not
look like my email was noticed by either maintainer and I did not pay
attention when the pull was sent since I was on CC.

Fixes: c6570114 ("Merge tag 'rproc-v5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc")
Link: https://lore.kernel.org/lkml/20200327185055.GA22438@ubuntu-m2-xlarge-x86/


Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

commit 02e6d546

 upstream.

dm timer ops set_load() api allows to configure the load value and to
set the auto reload feature. But auto reload feature is independent of
load value and should be part of configuring pwm. This way pwm can be
disabled by disabling auto reload feature using set_pwm() so that the
current pwm cycle will be completed. Else pwm disabling causes the
cycle to be stopped abruptly.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200305082715.15861-7-lokeshvutla@ti.com

commit 92fd8686

 upstream.

omap_dm_timer_ops provide support to configure the pwm but there is no
support to get the current status. For configuring pwm it is advised to
check the current hw status instead of relying on pwm framework. So
implement a new timer ops to get the current status of pwm.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tony Lindgen <tony@atomide.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200305082715.15861-6-lokeshvutla@ti.com

commit aff7665d

 upstream.

Write to trigger register(OMAP_TIMER_TRIGGER_REG) will load the value
in Load register(OMAP_TIMER_LOAD_REG) into Counter register
(OMAP_TIMER_COUNTER_REG).

omap_dm_timer_set_load() writes into trigger register every time load
register is updated. When timer is configured in pwm mode, this causes
disruption in current pwm cycle, which is not expected especially when
pwm is used as PPS signal for synchronized PTP clocks. So do not write
into trigger register on updating the period.

Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200305082715.15861-5-lokeshvutla@ti.com

commit b34677b0

 upstream.

omap_dm_timer_enable() restores the entire context(including counter)
based on 2 conditions:
- If get_context_loss_count is populated and context is lost.
- If get_context_loss_count is not populated update unconditionally.

Case2 has a side effect of updating the counter register even though
context is not lost. When timer is configured in pwm mode, this is
causing undesired behaviour in the pwm period.

Instead of using get_context_loss_count call back, implement cpu_pm
notifier with context save and restore support. And delete the
get_context_loss_count callback all together.

Suggested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[tony@atomide.com: removed pm_runtime calls from cpuidle calls]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200316111453.15441-1-lokeshvutla@ti.com

commit 5e20931c

 upstream.

Let's add runtime_suspend and resume functions and atomic enabled
flag. This way we can use these when converting to use cpuidle
for saving and restoring device context.

And we need to maintain the driver state in the driver as documented
in "9. Autosuspend, or automatically-delayed suspends" in the
Documentation/power/runtime_pm.rst document related to using driver
private lock and races with runtime_suspend().

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200305082715.15861-3-lokeshvutla@ti.com

commit 341e8cba

 upstream.

Use SPDX-License-Identifier instead of a verbose license text.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Link: https://lore.kernel.org/r/20200305082715.15861-2-lokeshvutla@ti.com

SYSFW ABI 3.0 introduced non compatible changes in order to support SR2.0
of am654.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

In the unlikely event of channel request failure the code should check
the failed channel against error code.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>

Add DT node for the Texas Instruments K3 Multicore J721E SoC platforms
chipid module.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

Add DT node for the Texas Instruments K3 Multicore AM65x SoC platforms
chipid module.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

Select TI chip id driver for TI's SoCs based on K3 architecture to provide
this information to user space and Kernel as it is required by other
drivers to determine SoC revision to function properly.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

The Texas Instruments K3 Multicore SoC platforms have chipid module which
is represented by CTRLMMR_xxx_JTAGID register and contains information
about SoC id and revision.
 Bits:
  31-28 VARIANT Device variant
  27-12 PARTNO  Part number
  11-1  MFG     Indicates TI as manufacturer (0x17)
  1             Always 1

This patch adds corresponding driver to identify the TI K3 SoC family and
revision, and registers this information with the SoC bus. It is available
under /sys/devices/soc0/ for user space, and can be checked, where needed,
in Kernel using soc_device_match().

Identification is done by:
- checking MFG to be TI ID
 - retrieving Device variant (revision)
 - retrieving Part number and convert it to the family
 - retrieving machine from DT "/model"

Example J721E:
  # cat /sys/devices/soc0/{machine,family,revision}
  Texas Instruments K3 J721E SoC
  J721E
  SR1.0

Example AM65x:
  # cat /sys/devices/soc0/{machine,family,revision}
  Texas Instruments AM654 Base Board
  AM65X
  SR1.0

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

Add DT binding for Texas Instruments K3 Multicore SoC platforms chipid
module which is represented by CTRLMMR_xxx_JTAGID register and contains
information about SoC id and revision.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>

TI-Feature: connectivity
TI-Branch: connectivity-ti-linux-5.4.y

* 'connectivity-ti-linux-5.4.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity

:
  ti_config_fragments/connectivity.cfg: Enable flower classifier
  net: ti: prueth_core: Add Broadcast, Multicast and Unicast storm prevention support
  net: ti: prueth_core: Move struct definition to prueth.h

Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>

Enable Flower classifer to support ingress storm prevention feature of
ICSSM PRU ethernet

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>

Prueth firmware on AM57xx, AM43xx and AM33xx supports credit based
broadcast, multicast and unicast storm prevention counter. There are
separate counters provided for each of them. Driver writes number of
packets allowed in a 100ms interval. When firmware encounters
packet of a given type, it decrements the value by 1 and when the
counter reaches 0, further packets are dropped.

So, add a way to set limit on number of broadcast, multicast and unicast
packets (L2 level) using the counters supported by firmware.
This is done by implementing offloading of tc-flower policer in
ndo_setup_tc() callback.

tc filter sets rate limit in terms of bits per second but firmware
supports limiting in terms of credits where each credit is equal to one
ethernet packet. Therefore, driver converts bits per second limit to
number of packets per second assuming minimum ethernet frame size for
each packet (Using min frame size allows much granular packets per
second setting)
There is a periodic hrtimer task that runs every 100ms refreshing
available credits. For simplicity credits are divided equally for each
100ms interval.

Based on https://lore.kernel.org/patchwork/patch/1217254/



Example for adding different filters:

Broadcast (dst mac is all 0xffs):
tc qdisc add dev eth2 clsact
tc filter add dev eth2 ingress flower skip_sw dst_mac ff:ff:ff:ff:ff:ff action police rate 10kbit burst 64k

Multicast (dst mac addr has first bit set, below is just an example):
tc qdisc add dev eth2 clsact
tc filter add dev eth2 ingress flower skip_sw dst_mac 01:00:00:00:00:00 action police rate 10kbit burst 64k

Unicast (dst mac addr where first bit is not set, below is just an example):
tc qdisc add dev eth2 clsact
tc filter add dev eth2 ingress flower skip_sw dst_mac 34:10:31:12:11:45 action police rate 10kbit burst 64k

Note that the unicast filter applies to all ingress traffic irrespective of
src mac. Also note that the dst_mac specified in above rule need not be
same as port's mac address. Any non multicast, non broadcast mac address will
end up setting the unicast filter.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>

Move core structs into prueth.h This is in preparation to adding storm
prevention support using a separate .c file.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>

TI-Feature: connectivity
TI-Branch: connectivity-ti-linux-5.4.y

* 'connectivity-ti-linux-5.4.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity

:
  media: ov5640: adjust htot
  drm/tidss: remove AM65x PG1 YUV erratum code
  ARM: dts: dra7: Fix bus_dma_limit for PCIe2

Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>

Merge branch 'ti/5.4-pull' of https://bitbucket.itg.ti.com/scm/~a0400822/linux into connectivity-ti-linux-5.4.y

Adjust htot for most of the modes. The numbers are from the OV5640
datasheet, and with these the driver works more reliably on DRA76 EVM +
OV5640, using 2 datalanes.

Without the patch, I see often ComplexIO (i.e. PHY) errors when
starting the streaming, and 1280x720 does not work at all without this
change.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

AM65x PG1 has a HW issue with YUV pixel formats, resulting in wrong
colors on the screen. This issue is fixed in PG2 hardware.

The driver currently has code to hide YUV pixel formats from the
userspace. To support PG2, we would need to add code to detect the SoC
version and hide the YUV formats based on that.

However, as PG1 will be phased out and PG2 will be the main platform, a
much simpler solution is just to drop the code in question. The downside
is that the users will be able to use YUV formats on PG1, getting wrong
colors on the screen. On the other hand, that may also be a plus, as the
same applications will now work on PG1 and PG2, even if the colors are
wrong on PG1.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

TI-Feature: platform_base
TI-Branch: platform-ti-linux-5.4.y

* 'platform-ti-linux-5.4.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform

:
  arm64: dts: ti: k3-am654-base-board: Fix mailbox0_cluster1 interrupt

Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>

The Mailbox Cluster1 interrupt on Linux uses the first interrupt output
line from the cluster. The current interrupt number of 431 is off by 1,
it represents the last interrupt output line #3 from Mailbox Cluster2.
Fix this properly to re-enable the mailbox communications with the R5F
Core1.

Fixes: 2a1ad598

 ("arm64: dts: k3-am65: ti-sci-inta/intr: Update to latest bindings")
Signed-off-by: Suman Anna <s-anna@ti.com>

Kishon Vijay Abraham I authored 5 years ago and Vignesh Raghavendra committed 5 years ago

Even though commit 327335bd

 ("ARM: dts: dra7: Add bus_dma_limit
for L3 bus") added bus_dma_limit for L3 bus, the PCIe controller
gets incorrect value of bus_dma_limit.

Fix it by adding empty dma-ranges property to axi@1
(parent device tree node of PCIe controller).

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

TI-Feature: connectivity
TI-Branch: connectivity-ti-linux-5.4.y

* 'connectivity-ti-linux-5.4.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity

:
  net: ethernet: ti: am65-cpsw-nuss: fix irqs type
  dma-direct: Fix data truncation in dma_direct_get_required_mask()
  ARM: dts: dra7: Fix bus_dma_limit for PCIe

Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>

TI-Feature: platform_base
TI-Branch: platform-ti-linux-5.4.y

* 'platform-ti-linux-5.4.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform

:
  irqchip/ti-sci-inta: fix processing of masked irqs
  arm64: dts: k3-am654-base-board-jailhouse: Disable mcu_uart0
  misc: sram: dma-heap-export: Fix memory leak in dma-buf attach
  dmaengine: ti: k3-udma: Implement support for atype (for virtualization)
  dt-bindings: dma: ti: k3-udma: Update for atype support (virtualization)

Signed-off-by: LCPD Auto Merger <lcpd_integration@list.ti.com>

Grygorii Strashko authored 5 years ago and Vignesh Raghavendra committed 5 years ago

The K3 INTA driver, which is source TX/RX IRQs for CPSW NUSS, defines IRQs
triggering type as EDGE by default, but triggering type for CPSW NUSS TX/RX
IRQs has to be LEVEL as the EDGE triggering type may cause unnecessary IRQs
triggering and NAPI scheduling for empty queues.

Fix it by explicitly specifying CPSW NUSS TX/RX IRQ type as
IRQF_TRIGGER_HIGH.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Kishon Vijay Abraham I authored 5 years ago and Vignesh Raghavendra committed 5 years ago

The upper 32-bit physical address gets truncated inadvertently
when dma_direct_get_required_mask() invokes phys_to_dma_direct().
This results in dma_addressing_limited() return incorrect value
when used in platforms with LPAE enabled.
Fix it here by explicitly type casting 'max_pfn' to phys_addr_t
in order to prevent overflow of intermediate value while evaluating
'(max_pfn - 1) << PAGE_SHIFT'.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Kishon Vijay Abraham I authored 5 years ago and Vignesh Raghavendra committed 5 years ago

Even though commit 327335bd

 ("ARM: dts: dra7: Add bus_dma_limit
for L3 bus") added bus_dma_limit for L3 bus, the PCIe controller
gets incorrect value of bus_dma_limit.

Fix it by adding empty dma-ranges property to axi@0 and axi@1
(parent device tree node of PCIe controller).

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

The ti_sci_inta_irq_handler() does not take into account INTA IRQs state
(masked/unmasked) as it uses INTA_STATUS_CLEAR_j register to get INTA IRQs
status, which provides raw status value.
This causes hard IRQ handlers to be called or threaded handlers to be
scheduled many times even if corresponding INTA IRQ is masked.
Above, first of all, affects, LEVEL interrupts processing and causes
unexpected behavior up the system stack or crash.

Fix it by using the Interrupt Masked Status INTA_STATUSM_j register which
provides masked INTA IRQs status.

Fixes: 9f1463b8

 ("irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>

When using Jailhouse hypervisor, the mcu_uart0 is being used by
other virtual machines non root cells.

Disable this from the root cell DTS overlay.

Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>