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Commit dd2d4819 authored by Robert Nelson's avatar Robert Nelson
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pinmux: bbai64 cleanups 


Signed-off-by: default avatarRobert Nelson <robertcnelson@gmail.com>
parent 03b26056
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pinmux/bbai64.sh
+ 7
− 7
View file @ dd2d4819
......@@ -88,13 +88,13 @@ label="P8_38A" ; ball="AJ20" ; sch="P8_38A" ; find_pin
label="P8_38B" ; ball="Y29" ; sch="P8_38B" ; find_pin
label="P8_39" ; ball="AC26" ; sch="P8_39" ; find_pin
label="p8_40" ; ball="AA24" ; sch="AA24_PRG0_PRU1_GPO7" ; find_pin
label="p8_41" ; ball="AD29" ; sch="AD29_PRG0_PRU1_GPO4" ; find_pin
label="p8_42" ; ball="AB27" ; sch="AB27_SYS_BOOTMODE6" ; find_pin
label="p8_43" ; ball="AD27" ; sch="AD27_PRG0_PRU1_GPO2" ; find_pin
label="p8_44" ; ball="AC25" ; sch="AC25_PRG0_PRU1_GPO3" ; find_pin
label="p8_45" ; ball="AG29" ; sch="AG29_PRG0_PRU1_GPO16" ; find_pin
label="p8_46" ; ball="Y25" ; sch="Y25_SYS_BOOTMODE3" ; find_pin
label="P8_40" ; ball="AA24" ; sch="P8_40" ; find_pin
label="P8_41" ; ball="AD29" ; sch="P8_41" ; find_pin
label="P8_42" ; ball="AB27" ; sch="P8_42" ; find_pin
label="P8_43" ; ball="AD27" ; sch="P8_43" ; find_pin
label="P8_44" ; ball="AC25" ; sch="P8_44" ; find_pin
label="P8_45" ; ball="AG29" ; sch="P8_45" ; find_pin
label="P8_46" ; ball="Y25" ; sch="P8_46" ; find_pin
label="p9_11" ; ball="AC23" ; sch="AC23_UART0_RXD" ; find_pin
label="p9_12" ; ball="AE27" ; sch="AE27_MCASP0_ACLKR" ; find_pin
......
pinmux/board/bbai64/bbai64-bone-pins.h
+ 14
− 14
View file @ dd2d4819
......@@ -43,13 +43,13 @@
#define gpio_p8_38a &main_gpio0 9 /* AJ20: PRG1_PRU0_GPO8 P8_38A */
#define gpio_p8_38b &main_gpio0 105 /* Y29: RGMII6_RD3 P8_38B */
#define gpio_p8_39 &main_gpio0 69 /* AC26: PRG0_PRU1_GPO6 P8_39 */
#define gpio_p8_40 &main_gpio0 70 /* AA24: PRG0_PRU1_GPO7 AA24_PRG0_PRU1_GPO7 */
#define gpio_p8_41 &main_gpio0 67 /* AD29: PRG0_PRU1_GPO4 AD29_PRG0_PRU1_GPO4 */
#define gpio_p8_42 &main_gpio0 68 /* AB27: PRG0_PRU1_GPO5 AB27_SYS_BOOTMODE6 */
#define gpio_p8_43 &main_gpio0 65 /* AD27: PRG0_PRU1_GPO2 AD27_PRG0_PRU1_GPO2 */
#define gpio_p8_44 &main_gpio0 66 /* AC25: PRG0_PRU1_GPO3 AC25_PRG0_PRU1_GPO3 */
#define gpio_p8_45 &main_gpio0 79 /* AG29: PRG0_PRU1_GPO16 AG29_PRG0_PRU1_GPO16 */
#define gpio_p8_46 &main_gpio0 80 /* Y25: PRG0_PRU1_GPO17 Y25_SYS_BOOTMODE3 */
#define gpio_p8_40 &main_gpio0 70 /* AA24: PRG0_PRU1_GPO7 P8_40 */
#define gpio_p8_41 &main_gpio0 67 /* AD29: PRG0_PRU1_GPO4 P8_41 */
#define gpio_p8_42 &main_gpio0 68 /* AB27: PRG0_PRU1_GPO5 P8_42 */
#define gpio_p8_43 &main_gpio0 65 /* AD27: PRG0_PRU1_GPO2 P8_43 */
#define gpio_p8_44 &main_gpio0 66 /* AC25: PRG0_PRU1_GPO3 P8_44 */
#define gpio_p8_45 &main_gpio0 79 /* AG29: PRG0_PRU1_GPO16 P8_45 */
#define gpio_p8_46 &main_gpio0 80 /* Y25: PRG0_PRU1_GPO17 P8_46 */
#define gpio_p9_11 &main_gpio0 1 /* AC23: PRG1_PRU0_GPO0 AC23_UART0_RXD */
#define gpio_p9_12 &main_gpio0 45 /* AE27: PRG0_PRU0_GPO2 AE27_MCASP0_ACLKR */
#define gpio_p9_13 &main_gpio0 2 /* AG22: PRG1_PRU0_GPO1 AG22_UART0_TXD */
......@@ -154,13 +154,13 @@
#define p8_38a(mode, mux) J721E_IOPAD(0x24, mode, mux) /* AJ20: PRG1_PRU0_GPO8 P8_38A */
#define p8_38b(mode, mux) J721E_IOPAD(0x1A8, mode, mux) /* Y29: RGMII6_RD3 P8_38B */
#define p8_39(mode, mux) J721E_IOPAD(0x118, mode, mux) /* AC26: PRG0_PRU1_GPO6 P8_39 */
#define p8_40(mode, mux) J721E_IOPAD(0x11C, mode, mux) /* AA24: PRG0_PRU1_GPO7 AA24_PRG0_PRU1_GPO7 */
#define p8_41(mode, mux) J721E_IOPAD(0x110, mode, mux) /* AD29: PRG0_PRU1_GPO4 AD29_PRG0_PRU1_GPO4 */
#define p8_42(mode, mux) J721E_IOPAD(0x114, mode, mux) /* AB27: PRG0_PRU1_GPO5 AB27_SYS_BOOTMODE6 */
#define p8_43(mode, mux) J721E_IOPAD(0x108, mode, mux) /* AD27: PRG0_PRU1_GPO2 AD27_PRG0_PRU1_GPO2 */
#define p8_44(mode, mux) J721E_IOPAD(0x10C, mode, mux) /* AC25: PRG0_PRU1_GPO3 AC25_PRG0_PRU1_GPO3 */
#define p8_45(mode, mux) J721E_IOPAD(0x140, mode, mux) /* AG29: PRG0_PRU1_GPO16 AG29_PRG0_PRU1_GPO16 */
#define p8_46(mode, mux) J721E_IOPAD(0x144, mode, mux) /* Y25: PRG0_PRU1_GPO17 Y25_SYS_BOOTMODE3 */
#define p8_40(mode, mux) J721E_IOPAD(0x11C, mode, mux) /* AA24: PRG0_PRU1_GPO7 P8_40 */
#define p8_41(mode, mux) J721E_IOPAD(0x110, mode, mux) /* AD29: PRG0_PRU1_GPO4 P8_41 */
#define p8_42(mode, mux) J721E_IOPAD(0x114, mode, mux) /* AB27: PRG0_PRU1_GPO5 P8_42 */
#define p8_43(mode, mux) J721E_IOPAD(0x108, mode, mux) /* AD27: PRG0_PRU1_GPO2 P8_43 */
#define p8_44(mode, mux) J721E_IOPAD(0x10C, mode, mux) /* AC25: PRG0_PRU1_GPO3 P8_44 */
#define p8_45(mode, mux) J721E_IOPAD(0x140, mode, mux) /* AG29: PRG0_PRU1_GPO16 P8_45 */
#define p8_46(mode, mux) J721E_IOPAD(0x144, mode, mux) /* Y25: PRG0_PRU1_GPO17 P8_46 */
#define p9_11(mode, mux) J721E_IOPAD(0x4, mode, mux) /* AC23: PRG1_PRU0_GPO0 AC23_UART0_RXD */
#define p9_12(mode, mux) J721E_IOPAD(0xB8, mode, mux) /* AE27: PRG0_PRU0_GPO2 AE27_MCASP0_ACLKR */
#define p9_13(mode, mux) J721E_IOPAD(0x8, mode, mux) /* AG22: PRG1_PRU0_GPO1 AG22_UART0_TXD */
......
pinmux/board/bbai64/bbai64-pinmux.dts
+ 31
− 31
View file @ dd2d4819
......@@ -1197,187 +1197,187 @@
>;
};
p8_40_gpio: p8-40-gpio-pins {
P8_40_gpio: P8-40-gpio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
>;
};
p8_40_gpio_pu: p8-40-gpio-pu-pins {
P8_40_gpio_pu: P8-40-gpio-pu-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x11C, PIN_INPUT_PULLUP, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
>;
};
p8_40_gpio_pd: p8-40-gpio-pd-pins {
P8_40_gpio_pd: P8-40-gpio-pd-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x11C, PIN_INPUT_PULLDOWN, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */
>;
};
p8_40_audio: p8-40-audio-pins {
P8_40_audio: P8-40-audio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x11C, PIN_INPUT, 12) /* (AA24) PRG0_PRU1_GPO7.MCASP1_AXR4 */
>;
};
p8_40_uart2_txd: p8-40-uart2-txd-pins {
P8_40_uart2_txd: P8-40-uart2-txd-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x11C, PIN_OUTPUT, 14) /* (AA24) PRG0_PRU1_GPO7.UART2_TXD */
>;
};
p8_41_gpio: p8-41-gpio-pins {
P8_41_gpio: P8-41-gpio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x110, PIN_INPUT, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */
>;
};
p8_41_gpio_pu: p8-41-gpio-pu-pins {
P8_41_gpio_pu: P8-41-gpio-pu-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x110, PIN_INPUT_PULLUP, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */
>;
};
p8_41_gpio_pd: p8-41-gpio-pd-pins {
P8_41_gpio_pd: P8-41-gpio-pd-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x110, PIN_INPUT_PULLDOWN, 7) /* (AD29) PRG0_PRU1_GPO4.GPIO0_67 */
>;
};
p8_41_audio: p8-41-audio-pins {
P8_41_audio: P8-41-audio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x110, PIN_INPUT, 12) /* (AD29) PRG0_PRU1_GPO4.MCASP1_AXR2 */
>;
};
p8_42_gpio: p8-42-gpio-pins {
P8_42_gpio: P8-42-gpio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x114, PIN_INPUT, 7) /* (AB27) PRG0_PRU1_GPO5.GPIO0_68 */
>;
};
p8_42_gpio_pu: p8-42-gpio-pu-pins {
P8_42_gpio_pu: P8-42-gpio-pu-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x114, PIN_INPUT_PULLUP, 7) /* (AB27) PRG0_PRU1_GPO5.GPIO0_68 */
>;
};
p8_42_gpio_pd: p8-42-gpio-pd-pins {
P8_42_gpio_pd: P8-42-gpio-pd-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x114, PIN_INPUT_PULLDOWN, 7) /* (AB27) PRG0_PRU1_GPO5.GPIO0_68 */
>;
};
p8_42_audio: p8-42-audio-pins {
P8_42_audio: P8-42-audio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x114, PIN_INPUT, 12) /* (AB27) PRG0_PRU1_GPO5.MCASP1_ACLKX */
>;
};
p8_43_gpio: p8-43-gpio-pins {
P8_43_gpio: P8-43-gpio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x108, PIN_INPUT, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */
>;
};
p8_43_gpio_pu: p8-43-gpio-pu-pins {
P8_43_gpio_pu: P8-43-gpio-pu-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x108, PIN_INPUT_PULLUP, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */
>;
};
p8_43_gpio_pd: p8-43-gpio-pd-pins {
P8_43_gpio_pd: P8-43-gpio-pd-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x108, PIN_INPUT_PULLDOWN, 7) /* (AD27) PRG0_PRU1_GPO2.GPIO0_65 */
>;
};
p8_43_audio: p8-43-audio-pins {
P8_43_audio: P8-43-audio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x108, PIN_INPUT, 12) /* (AD27) PRG0_PRU1_GPO2.MCASP1_ACLKR */
>;
};
p8_43_audio: p8-43-audio-pins {
P8_43_audio: P8-43-audio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x108, PIN_INPUT, 13) /* (AD27) PRG0_PRU1_GPO2.MCASP1_AXR10 */
>;
};
p8_44_gpio: p8-44-gpio-pins {
P8_44_gpio: P8-44-gpio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x10C, PIN_INPUT, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */
>;
};
p8_44_gpio_pu: p8-44-gpio-pu-pins {
P8_44_gpio_pu: P8-44-gpio-pu-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x10C, PIN_INPUT_PULLUP, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */
>;
};
p8_44_gpio_pd: p8-44-gpio-pd-pins {
P8_44_gpio_pd: P8-44-gpio-pd-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x10C, PIN_INPUT_PULLDOWN, 7) /* (AC25) PRG0_PRU1_GPO3.GPIO0_66 */
>;
};
p8_44_audio: p8-44-audio-pins {
P8_44_audio: P8-44-audio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x10C, PIN_INPUT, 12) /* (AC25) PRG0_PRU1_GPO3.MCASP1_AFSR */
>;
};
p8_44_audio: p8-44-audio-pins {
P8_44_audio: P8-44-audio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x10C, PIN_INPUT, 13) /* (AC25) PRG0_PRU1_GPO3.MCASP1_AXR11 */
>;
};
p8_45_gpio: p8-45-gpio-pins {
P8_45_gpio: P8-45-gpio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x140, PIN_INPUT, 7) /* (AG29) PRG0_PRU1_GPO16.GPIO0_79 */
>;
};
p8_45_gpio_pu: p8-45-gpio-pu-pins {
P8_45_gpio_pu: P8-45-gpio-pu-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x140, PIN_INPUT_PULLUP, 7) /* (AG29) PRG0_PRU1_GPO16.GPIO0_79 */
>;
};
p8_45_gpio_pd: p8-45-gpio-pd-pins {
P8_45_gpio_pd: P8-45-gpio-pd-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x140, PIN_INPUT_PULLDOWN, 7) /* (AG29) PRG0_PRU1_GPO16.GPIO0_79 */
>;
};
p8_45_audio: p8-45-audio-pins {
P8_45_audio: P8-45-audio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x140, PIN_INPUT, 12) /* (AG29) PRG0_PRU1_GPO16.MCASP2_AXR2 */
>;
};
p8_46_gpio: p8-46-gpio-pins {
P8_46_gpio: P8-46-gpio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x144, PIN_INPUT, 7) /* (Y25) PRG0_PRU1_GPO17.GPIO0_80 */
>;
};
p8_46_gpio_pu: p8-46-gpio-pu-pins {
P8_46_gpio_pu: P8-46-gpio-pu-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x144, PIN_INPUT_PULLUP, 7) /* (Y25) PRG0_PRU1_GPO17.GPIO0_80 */
>;
};
p8_46_gpio_pd: p8-46-gpio-pd-pins {
P8_46_gpio_pd: P8-46-gpio-pd-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x144, PIN_INPUT_PULLDOWN, 7) /* (Y25) PRG0_PRU1_GPO17.GPIO0_80 */
>;
};
p8_46_audio: p8-46-audio-pins {
P8_46_audio: P8-46-audio-pins {
pinctrl-single,pins = <
J721E_IOPAD(0x144, PIN_INPUT, 12) /* (Y25) PRG0_PRU1_GPO17.MCASP2_AXR3 */
>;
......
pinmux/board/bbai64/bbai64-pins.txt
+ 66
− 66
View file @ dd2d4819
......@@ -710,110 +710,110 @@ P8_39:GPIO0:AC26:GPIO0_69:7::
P8_39:GPMC0:AC26:GPMC0_A25:8::
P8_39:MCASP1:AC26:MCASP1_AXR3:12::
##################
p8_40
P8_40
debug-AA24-AA24-169
devicePinID_a=ID_3453,ball_a=AA24,powerDomainID_a=ID_3180
name_a=PRG0_PRU1_GPO7
controlRegisterOffset_a=0x11C
pupdStateDuringHHV_a=Z
p8_40:PRU_ICSSG0_PRU1:AA24:PRG0_PRU1_GPO7:0::
p8_40:PRU_ICSSG0_PRU1:AA24:PRG0_PRU1_GPI7:1::
p8_40:PRU_ICSSG0_IEP1:AA24:PRG0_IEP1_EDC_LATCH_IN1:2::
p8_40:SPI3:AA24:SPI3_CS0:4::
p8_40:MCAN11:AA24:MCAN11_TX:6::
p8_40:GPIO0:AA24:GPIO0_70:7::
p8_40:GPMC0:AA24:GPMC0_AD9:8::
p8_40:MCASP1:AA24:MCASP1_AXR4:12::
p8_40:USART2:AA24:UART2_TXD:14::
##################
p8_41
P8_40:PRU_ICSSG0_PRU1:AA24:PRG0_PRU1_GPO7:0::
P8_40:PRU_ICSSG0_PRU1:AA24:PRG0_PRU1_GPI7:1::
P8_40:PRU_ICSSG0_IEP1:AA24:PRG0_IEP1_EDC_LATCH_IN1:2::
P8_40:SPI3:AA24:SPI3_CS0:4::
P8_40:MCAN11:AA24:MCAN11_TX:6::
P8_40:GPIO0:AA24:GPIO0_70:7::
P8_40:GPMC0:AA24:GPMC0_AD9:8::
P8_40:MCASP1:AA24:MCASP1_AXR4:12::
P8_40:USART2:AA24:UART2_TXD:14::
##################
P8_41
debug-AD29-AD29-166
devicePinID_a=ID_3428,ball_a=AD29,powerDomainID_a=ID_3180
name_a=PRG0_PRU1_GPO4
controlRegisterOffset_a=0x110
pupdStateDuringHHV_a=Z
p8_41:PRU_ICSSG0_PRU1:AD29:PRG0_PRU1_GPO4:0::
p8_41:PRU_ICSSG0_PRU1:AD29:PRG0_PRU1_GPI4:1::
p8_41:PRU_ICSSG0_RGMII2:AD29:PRG0_RGMII2_RX_CTL:2::
p8_41:PRU_ICSSG0_PWM2:AD29:PRG0_PWM2_B2:3::
p8_41:RGMII4:AD29:RGMII4_RX_CTL:4::
p8_41:RMII4:AD29:RMII4_TXD1:5::
p8_41:GPIO0:AD29:GPIO0_67:7::
p8_41:GPMC0:AD29:GPMC0_A24:8::
p8_41:MCASP1:AD29:MCASP1_AXR2:12::
##################
p8_42
P8_41:PRU_ICSSG0_PRU1:AD29:PRG0_PRU1_GPO4:0::
P8_41:PRU_ICSSG0_PRU1:AD29:PRG0_PRU1_GPI4:1::
P8_41:PRU_ICSSG0_RGMII2:AD29:PRG0_RGMII2_RX_CTL:2::
P8_41:PRU_ICSSG0_PWM2:AD29:PRG0_PWM2_B2:3::
P8_41:RGMII4:AD29:RGMII4_RX_CTL:4::
P8_41:RMII4:AD29:RMII4_TXD1:5::
P8_41:GPIO0:AD29:GPIO0_67:7::
P8_41:GPMC0:AD29:GPMC0_A24:8::
P8_41:MCASP1:AD29:MCASP1_AXR2:12::
##################
P8_42
debug-AB27-AB27-167
devicePinID_a=ID_3438,ball_a=AB27,powerDomainID_a=ID_3180
name_a=PRG0_PRU1_GPO5
controlRegisterOffset_a=0x114
pupdStateDuringHHV_a=Z
p8_42:PRU_ICSSG0_PRU1:AB27:PRG0_PRU1_GPO5:0::
p8_42:PRU_ICSSG0_PRU1:AB27:PRG0_PRU1_GPI5:1::
p8_42:GPIO0:AB27:GPIO0_68:7::
p8_42:GPMC0:AB27:GPMC0_AD8:8::
p8_42:MCASP1:AB27:MCASP1_ACLKX:12::
P8_42:PRU_ICSSG0_PRU1:AB27:PRG0_PRU1_GPO5:0::
P8_42:PRU_ICSSG0_PRU1:AB27:PRG0_PRU1_GPI5:1::
P8_42:GPIO0:AB27:GPIO0_68:7::
P8_42:GPMC0:AB27:GPMC0_AD8:8::
P8_42:MCASP1:AB27:MCASP1_ACLKX:12::
##################
p8_43
P8_43
debug-AD27-AD27-164
devicePinID_a=ID_3408,ball_a=AD27,powerDomainID_a=ID_3180
name_a=PRG0_PRU1_GPO2
controlRegisterOffset_a=0x108
pupdStateDuringHHV_a=Z
p8_43:PRU_ICSSG0_PRU1:AD27:PRG0_PRU1_GPO2:0::
p8_43:PRU_ICSSG0_PRU1:AD27:PRG0_PRU1_GPI2:1::
p8_43:PRU_ICSSG0_RGMII2:AD27:PRG0_RGMII2_RD2:2::
p8_43:PRU_ICSSG0_PWM2:AD27:PRG0_PWM2_A2:3::
p8_43:RGMII4:AD27:RGMII4_RD2:4::
p8_43:RMII4:AD27:RMII4_CRS_DV:5::
p8_43:GPIO0:AD27:GPIO0_65:7::
p8_43:GPMC0:AD27:GPMC0_A23:8::
p8_43:MCASP1:AD27:MCASP1_ACLKR:12::
p8_43:MCASP1:AD27:MCASP1_AXR10:13::
##################
p8_44
P8_43:PRU_ICSSG0_PRU1:AD27:PRG0_PRU1_GPO2:0::
P8_43:PRU_ICSSG0_PRU1:AD27:PRG0_PRU1_GPI2:1::
P8_43:PRU_ICSSG0_RGMII2:AD27:PRG0_RGMII2_RD2:2::
P8_43:PRU_ICSSG0_PWM2:AD27:PRG0_PWM2_A2:3::
P8_43:RGMII4:AD27:RGMII4_RD2:4::
P8_43:RMII4:AD27:RMII4_CRS_DV:5::
P8_43:GPIO0:AD27:GPIO0_65:7::
P8_43:GPMC0:AD27:GPMC0_A23:8::
P8_43:MCASP1:AD27:MCASP1_ACLKR:12::
P8_43:MCASP1:AD27:MCASP1_AXR10:13::
##################
P8_44
debug-AC25-AC25-165
devicePinID_a=ID_3419,ball_a=AC25,powerDomainID_a=ID_3180
name_a=PRG0_PRU1_GPO3
controlRegisterOffset_a=0x10C
pupdStateDuringHHV_a=Z
p8_44:PRU_ICSSG0_PRU1:AC25:PRG0_PRU1_GPO3:0::
p8_44:PRU_ICSSG0_PRU1:AC25:PRG0_PRU1_GPI3:1::
p8_44:PRU_ICSSG0_RGMII2:AC25:PRG0_RGMII2_RD3:2::
p8_44:RGMII4:AC25:RGMII4_RD3:4::
p8_44:RMII4:AC25:RMII4_RX_ER:5::
p8_44:GPIO0:AC25:GPIO0_66:7::
p8_44:MCASP1:AC25:MCASP1_AFSR:12::
p8_44:MCASP1:AC25:MCASP1_AXR11:13::
P8_44:PRU_ICSSG0_PRU1:AC25:PRG0_PRU1_GPO3:0::
P8_44:PRU_ICSSG0_PRU1:AC25:PRG0_PRU1_GPI3:1::
P8_44:PRU_ICSSG0_RGMII2:AC25:PRG0_RGMII2_RD3:2::
P8_44:RGMII4:AC25:RGMII4_RD3:4::
P8_44:RMII4:AC25:RMII4_RX_ER:5::
P8_44:GPIO0:AC25:GPIO0_66:7::
P8_44:MCASP1:AC25:MCASP1_AFSR:12::
P8_44:MCASP1:AC25:MCASP1_AXR11:13::
##################
p8_45
P8_45
debug-AG29-AG29-178
devicePinID_a=ID_3540,ball_a=AG29,powerDomainID_a=ID_3180
name_a=PRG0_PRU1_GPO16
controlRegisterOffset_a=0x140
pupdStateDuringHHV_a=Z
p8_45:PRU_ICSSG0_PRU1:AG29:PRG0_PRU1_GPO16:0::
p8_45:PRU_ICSSG0_PRU1:AG29:PRG0_PRU1_GPI16:1::
p8_45:PRU_ICSSG0_RGMII2:AG29:PRG0_RGMII2_TXC:2::
p8_45:PRU_ICSSG0_PWM1:AG29:PRG0_PWM1_A2:3::
p8_45:RGMII4:AG29:RGMII4_TXC:4::
p8_45:GPIO0:AG29:GPIO0_79:7::
p8_45:MCASP2:AG29:MCASP2_AXR2:12::
P8_45:PRU_ICSSG0_PRU1:AG29:PRG0_PRU1_GPO16:0::
P8_45:PRU_ICSSG0_PRU1:AG29:PRG0_PRU1_GPI16:1::
P8_45:PRU_ICSSG0_RGMII2:AG29:PRG0_RGMII2_TXC:2::
P8_45:PRU_ICSSG0_PWM1:AG29:PRG0_PWM1_A2:3::
P8_45:RGMII4:AG29:RGMII4_TXC:4::
P8_45:GPIO0:AG29:GPIO0_79:7::
P8_45:MCASP2:AG29:MCASP2_AXR2:12::
##################
p8_46
P8_46
debug-Y25-Y25-179
devicePinID_a=ID_3548,ball_a=Y25,powerDomainID_a=ID_3180
name_a=PRG0_PRU1_GPO17
controlRegisterOffset_a=0x144
pupdStateDuringHHV_a=Z
p8_46:PRU_ICSSG0_PRU1:Y25:PRG0_PRU1_GPO17:0::
p8_46:PRU_ICSSG0_PRU1:Y25:PRG0_PRU1_GPI17:1::
p8_46:PRU_ICSSG0_IEP1:Y25:PRG0_IEP1_EDC_SYNC_OUT1:2::
p8_46:PRU_ICSSG0_PWM1:Y25:PRG0_PWM1_B2:3::
p8_46:SPI3:Y25:SPI3_CLK:4::
p8_46:GPIO0:Y25:GPIO0_80:7::
p8_46:GPMC0:Y25:GPMC0_AD13:8::
p8_46:MCASP2:Y25:MCASP2_AXR3:12::
P8_46:PRU_ICSSG0_PRU1:Y25:PRG0_PRU1_GPO17:0::
P8_46:PRU_ICSSG0_PRU1:Y25:PRG0_PRU1_GPI17:1::
P8_46:PRU_ICSSG0_IEP1:Y25:PRG0_IEP1_EDC_SYNC_OUT1:2::
P8_46:PRU_ICSSG0_PWM1:Y25:PRG0_PWM1_B2:3::
P8_46:SPI3:Y25:SPI3_CLK:4::
P8_46:GPIO0:Y25:GPIO0_80:7::
P8_46:GPMC0:Y25:GPMC0_AD13:8::
P8_46:MCASP2:Y25:MCASP2_AXR3:12::
##################
p9_11
debug-AC23-AC23-100
......
pinmux/board/bbai64/bbai64.dts
+ 7
− 7
View file @ dd2d4819
......@@ -280,44 +280,44 @@
BONE_PIN(p8_39, gpio_pu, p8_39(PIN_INPUT_PULLUP, 7))
BONE_PIN(p8_39, gpio_pd, p8_39(PIN_INPUT_PULLDOWN, 7))
/* p8_40 (AA24) PRG0_PRU1_GPO7 (GPIO0_70) AA24_PRG0_PRU1_GPO7 */
/* p8_40 (AA24) PRG0_PRU1_GPO7 (GPIO0_70) P8_40 */
BONE_PIN(p8_40, default, p8_40(PIN_INPUT, ))
BONE_PIN(p8_40, gpio, p8_40(PIN_INPUT, 7))
BONE_PIN(p8_40, gpio_pu, p8_40(PIN_INPUT_PULLUP, 7))
BONE_PIN(p8_40, gpio_pd, p8_40(PIN_INPUT_PULLDOWN, 7))
BONE_PIN(p8_40, uart, p8_40(PIN_OUTPUT, 14)) /* UART2_TXD */
/* p8_41 (AD29) PRG0_PRU1_GPO4 (GPIO0_67) AD29_PRG0_PRU1_GPO4 */
/* p8_41 (AD29) PRG0_PRU1_GPO4 (GPIO0_67) P8_41 */
BONE_PIN(p8_41, default, p8_41(PIN_INPUT, ))
BONE_PIN(p8_41, gpio, p8_41(PIN_INPUT, 7))
BONE_PIN(p8_41, gpio_pu, p8_41(PIN_INPUT_PULLUP, 7))
BONE_PIN(p8_41, gpio_pd, p8_41(PIN_INPUT_PULLDOWN, 7))
/* p8_42 (AB27) PRG0_PRU1_GPO5 (GPIO0_68) AB27_SYS_BOOTMODE6 */
/* p8_42 (AB27) PRG0_PRU1_GPO5 (GPIO0_68) P8_42 */
BONE_PIN(p8_42, default, p8_42(PIN_INPUT, ))
BONE_PIN(p8_42, gpio, p8_42(PIN_INPUT, 7))
BONE_PIN(p8_42, gpio_pu, p8_42(PIN_INPUT_PULLUP, 7))
BONE_PIN(p8_42, gpio_pd, p8_42(PIN_INPUT_PULLDOWN, 7))
/* p8_43 (AD27) PRG0_PRU1_GPO2 (GPIO0_65) AD27_PRG0_PRU1_GPO2 */
/* p8_43 (AD27) PRG0_PRU1_GPO2 (GPIO0_65) P8_43 */
BONE_PIN(p8_43, default, p8_43(PIN_INPUT, ))
BONE_PIN(p8_43, gpio, p8_43(PIN_INPUT, 7))
BONE_PIN(p8_43, gpio_pu, p8_43(PIN_INPUT_PULLUP, 7))
BONE_PIN(p8_43, gpio_pd, p8_43(PIN_INPUT_PULLDOWN, 7))
/* p8_44 (AC25) PRG0_PRU1_GPO3 (GPIO0_66) AC25_PRG0_PRU1_GPO3 */
/* p8_44 (AC25) PRG0_PRU1_GPO3 (GPIO0_66) P8_44 */
BONE_PIN(p8_44, default, p8_44(PIN_INPUT, ))
BONE_PIN(p8_44, gpio, p8_44(PIN_INPUT, 7))
BONE_PIN(p8_44, gpio_pu, p8_44(PIN_INPUT_PULLUP, 7))
BONE_PIN(p8_44, gpio_pd, p8_44(PIN_INPUT_PULLDOWN, 7))
/* p8_45 (AG29) PRG0_PRU1_GPO16 (GPIO0_79) AG29_PRG0_PRU1_GPO16 */
/* p8_45 (AG29) PRG0_PRU1_GPO16 (GPIO0_79) P8_45 */
BONE_PIN(p8_45, default, p8_45(PIN_INPUT, ))
BONE_PIN(p8_45, gpio, p8_45(PIN_INPUT, 7))
BONE_PIN(p8_45, gpio_pu, p8_45(PIN_INPUT_PULLUP, 7))
BONE_PIN(p8_45, gpio_pd, p8_45(PIN_INPUT_PULLDOWN, 7))
/* p8_46 (Y25) PRG0_PRU1_GPO17 (GPIO0_80) Y25_SYS_BOOTMODE3 */
/* p8_46 (Y25) PRG0_PRU1_GPO17 (GPIO0_80) P8_46 */
BONE_PIN(p8_46, default, p8_46(PIN_INPUT, ))
BONE_PIN(p8_46, gpio, p8_46(PIN_INPUT, 7))
BONE_PIN(p8_46, gpio_pu, p8_46(PIN_INPUT_PULLUP, 7))
......
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