arm64: dts: ti: k3-j7200: Add SR2.0 SERDES changes

The SERDES in SR1.0 supports 2 reference clocks. The second
reference clock (core_ref1_clk) is hardwired to
MAIN_PLL3_HSDIV4_CLKOUT (100/125/156.25 MHz). DM firmware
update is required to set this clock to 156.25MHz for USXGMII
support.

Switch the SERDES wrapper device compatible to "ti,j7200-wiz-10g"
to be aware of the additional reference clock and the special
SCM register to manage the configuration i.e. "ti,scm" property.

Switch the SERDES device compatible to "ti,j7200-serdes-10g" to
support dual reference clock configurations.

The SERDES clock configuration is not changed in this patch.
Both the PLL reference clocks are still set to 100MHz (core_ref_clk)
i.e. MAIN_PLL2_HSDIV4_CLKOUT.
Later, when USXGMII is required the respective PLL reference
clock can be switched to (core_ref1_clk) i.e. 156.25MHz while
leaving the other PLL at 100MHz so PCIe/SGMII can continue to work.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>