- Oct 18, 2022
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Vignesh Raghavendra authored
commit 1607e6f9 upstream. Add pinctrl macros for AM62AX SoCs. These macro definitions are similar to that of previous platforms, but adding new definitions to avoid any naming confusions in the SoC dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Tested-by:
Devarsh Thakkar <devarsht@ti.com> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220901141328.899100-4-vigneshr@ti.com Signed-off-by:
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Vignesh Raghavendra authored
commit cad20a8d upstream. This adds bindings for TI's AM62A7 family of devices. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220901141328.899100-3-vigneshr@ti.com Signed-off-by:
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Vignesh Raghavendra authored
commit a3c52977 upstream. Rearrange SOC specific IOPAD macros alphabetically, so that its easier to read. No functional change intended. Signed-off-by:
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- Oct 12, 2022
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Vignesh Raghavendra authored
Merge tag 'v5.10.145' of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux into ti-linux-5.10.y-cicd This is the 5.10.145 stable release * tag 'v5.10.145' of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux: (260 commits) Linux 5.10.145 ALSA: hda/sigmatel: Fix unused variable warning for beep power change cgroup: Add missing cpus_read_lock() to cgroup_attach_task_all() video: fbdev: pxa3xx-gcu: Fix integer overflow in pxa3xx_gcu_write mksysmap: Fix the mismatch of 'L0' symbols in System.map MIPS: OCTEON: irq: Fix octeon_irq_force_ciu_mapping() afs: Return -EAGAIN, not -EREMOTEIO, when a file already locked net: usb: qmi_wwan: add Quectel RM520N ALSA: hda/tegra: Align BDL entry to 4KB boundary ALSA: hda/sigmatel: Keep power up while beep is enabled wifi: mac80211_hwsim: check length for virtio packets rxrpc: Fix calc of resend age rxrpc: Fix local destruction being repeated regulator: pfuze100: Fix the global-out-of-bounds access in pfuze100_regulator_pro...
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- Oct 11, 2022
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : arm64: dts: ti: k3-j784s4-evm: add USB SuperSpeed support arm64: dts: ti: Enable CAN interfaces for J784S4 EVM board net: ethernet: ti: cpsw-qos: Add support to taprio for past base_time arm64: dts: ti: am625-sk: Add overlay for HDMI audio arm64: dts: ti: am625-sk: Enable audio over HDMI PCI: j721e: correct lane count mask based on lane numbers Signed-off-by:
LCPD Auto Merger <lcpd_integration@list.ti.com>
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Enable USB 3.0 interface and its respective serdes settings, and required pinmuxing. Signed-off-by:
Matt Ranostay <mranostay@ti.com> Acked-by:
Hari Nagalla <hnagalla@ti.com> Signed-off-by:
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J784S4-EVM has several CAN bus interfaces on both MCU and MAIN domains. This enables the MCU domain interfaces, and the MAIN domain one that isn't muxed. Signed-off-by:
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If the base-time for taprio is in the past, start the schedule at the time of the form "base_time + N*cycle_time" where N is the smallest possible integer such that the above time is in the future. Signed-off-by:
Tanmay Patil <t-patil@ti.com> Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by:
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Enable audio output over HDMI instead of the 3.5mm jack. A FET switch (U65) on the EVM muxes serial audio lines coming from McASP between the codec (tlv320aic3106) and the HDMI bridge (sii9022). By default it uses the codec, but it can be toggled to use the HDMI bridge by shorting a (J24) header on the board. Signed-off-by:
Jai Luthra <j-luthra@ti.com> Tested-by:
Aradhya Bhatia <a-bhatia1@ti.com> Signed-off-by:
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The HDMI bridge driver supports receiving serial (i2s) audio from the SoC and transmitting it to the display for playback. Signed-off-by:
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Platforms that don't have 4x support have a single bit mask, and mask should based on the number of lanes that can be configured. Fixes: 719b08dc ("PCI: j721e: Add PCIe 4x lane selection support") Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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- Oct 06, 2022
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LCPD Auto Merger authored
TI-Feature: platform_base TI-Branch: platform-ti-linux-5.10.y * 'platform-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform : arm64: dts: ti: k3-am64-main: Fix the clock ID for rng node arm64: dts: ti: k3-j721s2-main: drop dma-coherent in crypto arm64: dts: ti: k3-j721e-main: crypto node cleanup arm64: dts: ti: k3-j7200-mcu: crypto node cleanup arm64: dts: ti: k3-am65-main: drop dma-coherent in crypto dt-bindings: crypto: ti,sa2ul: drop dma-coherent property Signed-off-by:
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Jayesh Choudhary authored
Fix the clock ID for rng node. It uses DEV_SA2_UL0_X1_CLK, not DEV_SA2_UL0_PKA_IN_CLK. Fixes: f54c8007 ('arm64: dts: ti: k3-am64-main: Enable crypto accelerator') Signed-off-by:
Jayesh Choudhary <j-choudhary@ti.com>
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Jayesh Choudhary authored
crypto driver itself is not dma-coherent. So drop it. Fixes: 0048b326 ('arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator') Signed-off-by:
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Jayesh Choudhary authored
crypto driver itself is not dma-coherent. So drop the dma-coherent property. Fix the clock ID for rng node. It uses DEV_SA2_UL0_X1_CLK, not DEV_SA2_UL0_PKA_IN_CLK. Fixes: 8ebcaaae ('arm64: dts: ti: k3-j721e-main: Add crypto accelerator node') Signed-off-by:
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Jayesh Choudhary authored
crypto driver itself is not dma-coherent. So drop the dma-coherent property. Fix the clock ID for rng node. It uses DEV_MCU_SA2_UL0_X1_CLK, not DEV_MCU_SA2_UL0_PKA_IN_CLK. Fixes: c32d4cb7 ('arm64: dts: ti: k3-j7200-mcu: Add the mcu sa2ul crypto node') Signed-off-by:
Andrew Davis <afd@ti.com>
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Jayesh Choudhary authored
crypto driver itself is not dma-coherent. So drop it. Fixes: b366b240 ('arm64: dts: ti: k3-am6: Add crypto accelarator node') Signed-off-by:
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Jayesh Choudhary authored
crypto driver itself is not dma-coherent. It is the system-dma that moves data and so 'dma-coherent' property should be dropped. Fixes: 2ce9a729 ('dt-bindings: crypto: Add TI SA2UL crypto accelerator documentation') Signed-off-by:
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- Sep 30, 2022
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : arm64: dts: ti: k3-j784s4-evm: Add DP1 arm64: dts: ti: k3-j784s4-evm: add DSI to eDP arm64: dts: ti: k3-j784s4-main: add DSI & DSI PHY drm/bridge: ti-sn65dsi86: Fix unbalanced pm_runtime state arm64: dts: ti: k3-j784s4-evm: Add DP0 arm64: dts: ti: k3-j784s4-*: add DP & DP PHY arm64: dts: ti: k3-j784s4-*: Add DSS node arm64: dts: ti: k3-j784s4-main: Enable crypto accelerator dmaengine: ti: k3-psil-j784s4: Add psil threads for sa2ul Signed-off-by:
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Add the endpoint nodes to describe connection from DSS => DSI Bridge => DSI to eDP bridge => eDP panel. Also set status of all the required nodes for DP1 as okay Signed-off-by:
Rahul T R <r-ravikumar@ti.com> Signed-off-by:
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Add DT nodes for DSI to eDP bridge. The DSI to edp bridge is sn65dsi86 on the board Signed-off-by:
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Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper. Signed-off-by:
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The commit 016204fe ("drm/bridge: ti-sn65dsi86: Detect id panel is connected") has added a pm_runtime_get_sync() call in the ti_sn_aux_transfer() function, and is expected to unwind before returning from the function. The logic erroneously added another pm_runtime_get_sync() instead of a pm_runtime_put_sync() call. Fix this. Fixes: 016204fe ("drm/bridge: ti-sn65dsi86: Detect id panel is connected") Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
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Add the endpoint nodes to describe connection from DSS => MHDP => DisplayPort connector. Also add the required nodes gpio expander 4 and pinmux for main_i2c4 which is required for controlling DP Power and set status of all the required nodes for DP0 as okay Signed-off-by:
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Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. Also add pinmux required for DP HPD. Signed-off-by:
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Add DSS node for J784S4 SoC. DSS IP in J784S4 is same as DSS IP in J721E, so same compatible is being used. Also add assigned clks for DSS Signed-off-by:
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Add the node for sa2ul crypto accelerator. Signed-off-by:
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Add endpoint configuration for the four ingress and two egress threads for main domain crypto accelerator. Signed-off-by:
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : (21 commits) arm64: dts: ti: k3-j784s4-evm: Enable TCA4608 I2C GPIO expander on main_i2c5 arm64: dts: ti: Add an overlay for Fusion board on J784S4 arm64: dts: ti: k3-j784s4-evm: Enable CSI2RX and corresponding DPHY instances arm64: dts: ti: k3-j784s4-evm: Enable main_i2c5 arm64: dts: ti: k3-j784s4-main: Add CSI2RX nodes arm64: dts: ti: k3-j784s4: Add initial PCIe/SerDes support for J784S4 arm64: dts: ti: k3-j784s4: Add overlay to enable CPSW9G ports in QSGMII mode arm64: dts: ti: j784s4-evm: Enable EthFw arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G arm64: dts: ti: k3-j784s4-mcu: Cleanup mcu_cpsw node arm64: dts: ti: k3-j784s4: Add MAIN CPSW2G node arm64: dts: ti: k3-j784s4: Add CPSW9G nodes arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes arm64: dts: ti: k3-j784s4-main: Add system controller node and SERDES lane mux net: ethernet: ti: am65-cpsw: Add support for J784s4 CPSW9G phy: ti: phy-gmii-sel: Add support for CPSW9G GMII SEL in J784s4 dmaengine: ti: k3-psil: Add PSI-L thread support for J784s4 soc: ti: k3-socinfo: Add entry for J784S4 SoC family dt-bindings: net: ti: k3-am654-cpsw-nuss: Update bindings for J784S4 CPSW9G dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J784S4 ... Signed-off-by:
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Enable the TCA5608 I2C GPIO expander on main_i2c5 which provides the CSI2 expansion GPIOs on J784S4 EVM. Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by:
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The ADAS Sensor Fusion Application board can be used with J784S4 to connect up to 8 2MP cameras. Signed-off-by:
Pratyush Yadav <p.yadav@ti.com> Signed-off-by:
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CSI2RX and corresponding DPHY instances were disabled in the j784s4-main.dtsi, enable these instances. Signed-off-by:
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Enable the I2C instance and add pinmux entries for main_i2c5 which is the camera control interface for CSI. Signed-off-by:
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Add the entries for two CSI2RX instances and corresponding DPHY for J784S4 and keep them disabled by default. Signed-off-by:
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J784S4 SoC supports two PCIE instances as follows: * PCIE0 - 4x lanes * PCIE1 - 4x lanes J784S4 EVM board has the following PCIE connectors: * PCIE0 - 4x lanes * PCIE1 - 2x lanes Signed-off-by:
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The J7 Quad Port Add-On Ethernet Card for J784s4 Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode. Add support to reset PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses directly from U-Boot. Disable cpsw9g_virt_mac node in device-tree since native ethernet driver supports CPSW2G and CPSW9G. Replace j784s4-main-r5f0_0-fw which currently points to EthFw, with: pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f which is currently unused, to ensure that EthFw is not loaded. Signed-off-by:
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Add CPSW9G virt-mac nodes required by EthFw and enable the following nodes main_udmass_inta, main_ringacc and main_udmap required for communication between EthFw and virt-mac driver. Assign SerDes lane mapping required by EthFw. EthFw will be enabled by default with these changes. Signed-off-by:
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Enable MCU CPSW2G Signed-off-by:
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Cleanup mcu_cpsw node, by deleting "status = disabled" present within the "mdio@f00", "cpts@3d000" and "phy@4040" nodes for the following reasons: - Since the outer mcu_cpsw node is disabled by default, the inner "mdio@f00" and "cpts@3d000" nodes will also be disabled. - When the mcu_cpsw node is enabled, the "mdio@f00" node is also required to be enabled by default. - The "cpts@3d000" node does not have a label, so it will not be possible to enable it selectively when the mcu_cpsw node is enabled. - The "phy@4040" node is not a device. The cleanup will make the mcu_cpsw node similar to the main_cpsw0 and main_cpsw1 nodes. Signed-off-by:
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Add CPSW2G device tree node for the main domain CPSW2G and enable it. Signed-off-by:
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