- Oct 21, 2022
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Andrew Davis authored
4K pages are now the default, no need to explicitly set the same. Signed-off-by:Andrew Davis <afd@ti.com>
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- Oct 18, 2022
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LCPD Auto Merger authored
TI-Feature: platform_base TI-Branch: platform-ti-linux-5.10.y * 'platform-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform : dmaengine: k3-udma: Add system suspend/resume support arm64: dts: ti: k3-j784s4-*: Add GPU node arm64: dts: ti: Add support for AM62A7-SK arm64: dts: ti: Introduce AM62A7 family of SoCs dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62A dt-bindings: arm: ti: Add bindings for AM62A7 SoC dt-bindings: arm: ti: Rearrange IOPAD macros alphabetically Signed-off-by:
LCPD Auto Merger <lcpd_integration@list.ti.com>
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Vignesh Raghavendra authored
The K3 platforms configure the DMA resources with the help of the TI's System Firmware's Device Manager(DM) over TISCI. The group of DMA related Resource Manager[1] TISCI messages includes: INTA, RINGACC, UDMAP, and PSI-L. This configuration however, does not persist in the DM after leaving from Suspend-to-RAM state. We have to restore the DMA channel configuration over TISCI for all configured channels when entering suspend. The TISCI resource management calls for each DMA type (UDMA, PKTDMA, BCDMA) happen in device_free_chan_resources() and device_alloc_chan_resources(). In pm_suspend() we store the current udma_chan_config for channels that still have attached clients and call device_free_chan_resources(). In pm_resume() restore the udma_channel_config from backup and call device_alloc_chan_resources() for those channels. Drivers like CPSW do their own DMA resource management, so use the late system suspend/resume hooks. [1] https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/index.html#resource-management-rm Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> [g-vlaev@ti.com: Add udma_chan_config backup] [g-vlaev@ti.com: Supend only channels with clients] Signed-off-by:
Georgi Vlaev <g-vlaev@ti.com>
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Randolph Sapp authored
Add GPU node for J784S4 SoC and enable it in the k3-j784s4-evm.dtb. This is the same IMG BXS-4-64 core used in J721S2, so it shares the same compatible value and power domain names. Signed-off-by:
Randolph Sapp <rs@ti.com> Acked-by:
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Vignesh Raghavendra authored
commit 38c4a08c upstream. AM62A StarterKit (SK) board is a low cost, small form factor board designed for TI's AM62A7 SoC. It supports the following interfaces: * 2 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x1 HDMI Port with audio * x1 Headphone Jack * x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port * x1 UHS-1 capable µSD card slot * M.2 SDIO Wifi + UART slot * 1Gb OSPI NAND flash * x4 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin User Expansion Connector * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 20-pin header for Programmable Realtime Unit (PRU) IO pins * 40-pin CSI header Add basic support for AM62A7-SK. Schematics: https://www.ti.com/lit/zip/sprr459 Co-developed-by:
Bryan Brattlof <bb@ti.com> Signed-off-by:
Devarsh Thakkar <devarsht@ti.com> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220901141328.899100-6-vigneshr@ti.com Signed-off-by:
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Vignesh Raghavendra authored
commit 5fc6b1b6 upstream. The AM62A SoC belongs to the K3 Multicore SoC architecture platform that can run edge AI applications with Video/Vision processing. This provides advanced system integration with high security support to enable a broad set of applications in industrial/automotive markets such as, driver monitoring, machine vision, smart camera, eMirror, front camera, robotics, and building automation. Some highlights of AM62A SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortex-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * One AI accelerator (up to 2 TOPS), using one C7x256V DSP w/Matrix Multiplier accelerator (MMA) for Deep Learning usage. * VPAC3L(Vision Pre-processing Accelerator), providing 12-bit ISP up to 315MPixel/s RGB+IR support, and Noise Filter for improved integrated imaging and vision image processing. * H.264/H.265 Video Encode/Decode. + Motion JPEG encode * Display support, providing 24-bit RBG parallel interface up to 200MHz pixel clock support for 2K display resolution. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3x McASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment * One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design. More details about the SoCs can be found in the Technical Reference Manual: https://www.ti.com/lit/zip/spruj16 Co-developed-by:
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Vignesh Raghavendra authored
commit 1607e6f9 upstream. Add pinctrl macros for AM62AX SoCs. These macro definitions are similar to that of previous platforms, but adding new definitions to avoid any naming confusions in the SoC dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20220901141328.899100-4-vigneshr@ti.com Signed-off-by:
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Vignesh Raghavendra authored
commit cad20a8d upstream. This adds bindings for TI's AM62A7 family of devices. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220901141328.899100-3-vigneshr@ti.com Signed-off-by:
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Vignesh Raghavendra authored
commit a3c52977 upstream. Rearrange SOC specific IOPAD macros alphabetically, so that its easier to read. No functional change intended. Signed-off-by:
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- Oct 12, 2022
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Vignesh Raghavendra authored
Merge tag 'v5.10.145' of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux into ti-linux-5.10.y-cicd This is the 5.10.145 stable release * tag 'v5.10.145' of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux : (260 commits) Linux 5.10.145 ALSA: hda/sigmatel: Fix unused variable warning for beep power change cgroup: Add missing cpus_read_lock() to cgroup_attach_task_all() video: fbdev: pxa3xx-gcu: Fix integer overflow in pxa3xx_gcu_write mksysmap: Fix the mismatch of 'L0' symbols in System.map MIPS: OCTEON: irq: Fix octeon_irq_force_ciu_mapping() afs: Return -EAGAIN, not -EREMOTEIO, when a file already locked net: usb: qmi_wwan: add Quectel RM520N ALSA: hda/tegra: Align BDL entry to 4KB boundary ALSA: hda/sigmatel: Keep power up while beep is enabled wifi: mac80211_hwsim: check length for virtio packets rxrpc: Fix calc of resend age rxrpc: Fix local destruction being repeated regulator: pfuze100: Fix the global-out-of-bounds access in pfuze100_regulator_probe() ASoC: nau8824: Fix semaphore unbalance at error paths Revert "serial: 8250: Fix reporting real baudrate value in c_ospeed field" video: fbdev: i740fb: Error out if 'pixclock' equals zero tools/include/uapi: Fix <asm/errno.h> for parisc and xtensa cifs: don't send down the destination address to sendmsg for a SOCK_STREAM cifs: revalidate mapping when doing direct writes ... Signed-off-by:
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- Oct 11, 2022
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : arm64: dts: ti: k3-j784s4-evm: add USB SuperSpeed support arm64: dts: ti: Enable CAN interfaces for J784S4 EVM board net: ethernet: ti: cpsw-qos: Add support to taprio for past base_time arm64: dts: ti: am625-sk: Add overlay for HDMI audio arm64: dts: ti: am625-sk: Enable audio over HDMI PCI: j721e: correct lane count mask based on lane numbers Signed-off-by:
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Enable USB 3.0 interface and its respective serdes settings, and required pinmuxing. Signed-off-by:
Matt Ranostay <mranostay@ti.com> Acked-by:
Hari Nagalla <hnagalla@ti.com> Signed-off-by:
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J784S4-EVM has several CAN bus interfaces on both MCU and MAIN domains. This enables the MCU domain interfaces, and the MAIN domain one that isn't muxed. Signed-off-by:
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If the base-time for taprio is in the past, start the schedule at the time of the form "base_time + N*cycle_time" where N is the smallest possible integer such that the above time is in the future. Signed-off-by:
Tanmay Patil <t-patil@ti.com> Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by:
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Enable audio output over HDMI instead of the 3.5mm jack. A FET switch (U65) on the EVM muxes serial audio lines coming from McASP between the codec (tlv320aic3106) and the HDMI bridge (sii9022). By default it uses the codec, but it can be toggled to use the HDMI bridge by shorting a (J24) header on the board. Signed-off-by:
Jai Luthra <j-luthra@ti.com> Tested-by:
Aradhya Bhatia <a-bhatia1@ti.com> Signed-off-by:
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The HDMI bridge driver supports receiving serial (i2s) audio from the SoC and transmitting it to the display for playback. Signed-off-by:
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Platforms that don't have 4x support have a single bit mask, and mask should based on the number of lanes that can be configured. Fixes: 719b08dc ("PCI: j721e: Add PCIe 4x lane selection support") Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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- Oct 06, 2022
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LCPD Auto Merger authored
TI-Feature: platform_base TI-Branch: platform-ti-linux-5.10.y * 'platform-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform : arm64: dts: ti: k3-am64-main: Fix the clock ID for rng node arm64: dts: ti: k3-j721s2-main: drop dma-coherent in crypto arm64: dts: ti: k3-j721e-main: crypto node cleanup arm64: dts: ti: k3-j7200-mcu: crypto node cleanup arm64: dts: ti: k3-am65-main: drop dma-coherent in crypto dt-bindings: crypto: ti,sa2ul: drop dma-coherent property Signed-off-by:
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Jayesh Choudhary authored
Fix the clock ID for rng node. It uses DEV_SA2_UL0_X1_CLK, not DEV_SA2_UL0_PKA_IN_CLK. Fixes: f54c8007 ('arm64: dts: ti: k3-am64-main: Enable crypto accelerator') Signed-off-by:
Jayesh Choudhary <j-choudhary@ti.com>
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Jayesh Choudhary authored
crypto driver itself is not dma-coherent. So drop it. Fixes: 0048b326 ('arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator') Signed-off-by:
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Jayesh Choudhary authored
crypto driver itself is not dma-coherent. So drop the dma-coherent property. Fix the clock ID for rng node. It uses DEV_SA2_UL0_X1_CLK, not DEV_SA2_UL0_PKA_IN_CLK. Fixes: 8ebcaaae ('arm64: dts: ti: k3-j721e-main: Add crypto accelerator node') Signed-off-by:
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Jayesh Choudhary authored
crypto driver itself is not dma-coherent. So drop the dma-coherent property. Fix the clock ID for rng node. It uses DEV_MCU_SA2_UL0_X1_CLK, not DEV_MCU_SA2_UL0_PKA_IN_CLK. Fixes: c32d4cb7 ('arm64: dts: ti: k3-j7200-mcu: Add the mcu sa2ul crypto node') Signed-off-by:
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Jayesh Choudhary authored
crypto driver itself is not dma-coherent. So drop it. Fixes: b366b240 ('arm64: dts: ti: k3-am6: Add crypto accelarator node') Signed-off-by:
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Jayesh Choudhary authored
crypto driver itself is not dma-coherent. It is the system-dma that moves data and so 'dma-coherent' property should be dropped. Fixes: 2ce9a729 ('dt-bindings: crypto: Add TI SA2UL crypto accelerator documentation') Signed-off-by:
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- Sep 30, 2022
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : arm64: dts: ti: k3-j784s4-evm: Add DP1 arm64: dts: ti: k3-j784s4-evm: add DSI to eDP arm64: dts: ti: k3-j784s4-main: add DSI & DSI PHY drm/bridge: ti-sn65dsi86: Fix unbalanced pm_runtime state arm64: dts: ti: k3-j784s4-evm: Add DP0 arm64: dts: ti: k3-j784s4-*: add DP & DP PHY arm64: dts: ti: k3-j784s4-*: Add DSS node arm64: dts: ti: k3-j784s4-main: Enable crypto accelerator dmaengine: ti: k3-psil-j784s4: Add psil threads for sa2ul Signed-off-by:
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Add the endpoint nodes to describe connection from DSS => DSI Bridge => DSI to eDP bridge => eDP panel. Also set status of all the required nodes for DP1 as okay Signed-off-by:
Rahul T R <r-ravikumar@ti.com> Signed-off-by:
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Add DT nodes for DSI to eDP bridge. The DSI to edp bridge is sn65dsi86 on the board Signed-off-by:
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Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper. Signed-off-by:
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The commit 016204fe ("drm/bridge: ti-sn65dsi86: Detect id panel is connected") has added a pm_runtime_get_sync() call in the ti_sn_aux_transfer() function, and is expected to unwind before returning from the function. The logic erroneously added another pm_runtime_get_sync() instead of a pm_runtime_put_sync() call. Fix this. Fixes: 016204fe ("drm/bridge: ti-sn65dsi86: Detect id panel is connected") Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
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Add the endpoint nodes to describe connection from DSS => MHDP => DisplayPort connector. Also add the required nodes gpio expander 4 and pinmux for main_i2c4 which is required for controlling DP Power and set status of all the required nodes for DP0 as okay Signed-off-by:
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Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. Also add pinmux required for DP HPD. Signed-off-by:
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Add DSS node for J784S4 SoC. DSS IP in J784S4 is same as DSS IP in J721E, so same compatible is being used. Also add assigned clks for DSS Signed-off-by:
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Add the node for sa2ul crypto accelerator. Signed-off-by:
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Add endpoint configuration for the four ingress and two egress threads for main domain crypto accelerator. Signed-off-by:
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : (21 commits) arm64: dts: ti: k3-j784s4-evm: Enable TCA4608 I2C GPIO expander on main_i2c5 arm64: dts: ti: Add an overlay for Fusion board on J784S4 arm64: dts: ti: k3-j784s4-evm: Enable CSI2RX and corresponding DPHY instances arm64: dts: ti: k3-j784s4-evm: Enable main_i2c5 arm64: dts: ti: k3-j784s4-main: Add CSI2RX nodes arm64: dts: ti: k3-j784s4: Add initial PCIe/SerDes support for J784S4 arm64: dts: ti: k3-j784s4: Add overlay to enable CPSW9G ports in QSGMII mode arm64: dts: ti: j784s4-evm: Enable EthFw arm64: dts: ti: k3-j784s4-evm: Enable MCU CPSW2G arm64: dts: ti: k3-j784s4-mcu: Cleanup mcu_cpsw node arm64: dts: ti: k3-j784s4: Add MAIN CPSW2G node arm64: dts: ti: k3-j784s4: Add CPSW9G nodes arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes arm64: dts: ti: k3-j784s4-main: Add system controller node and SERDES lane mux net: ethernet: ti: am65-cpsw: Add support for J784s4 CPSW9G phy: ti: phy-gmii-sel: Add support for CPSW9G GMII SEL in J784s4 dmaengine: ti: k3-psil: Add PSI-L thread support for J784s4 soc: ti: k3-socinfo: Add entry for J784S4 SoC family dt-bindings: net: ti: k3-am654-cpsw-nuss: Update bindings for J784S4 CPSW9G dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J784S4 ... Signed-off-by:
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Enable the TCA5608 I2C GPIO expander on main_i2c5 which provides the CSI2 expansion GPIOs on J784S4 EVM. Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by:
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The ADAS Sensor Fusion Application board can be used with J784S4 to connect up to 8 2MP cameras. Signed-off-by:
Pratyush Yadav <p.yadav@ti.com> Signed-off-by:
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CSI2RX and corresponding DPHY instances were disabled in the j784s4-main.dtsi, enable these instances. Signed-off-by:
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Enable the I2C instance and add pinmux entries for main_i2c5 which is the camera control interface for CSI. Signed-off-by:
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Add the entries for two CSI2RX instances and corresponding DPHY for J784S4 and keep them disabled by default. Signed-off-by:
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