codec: audio: add codec driver for Lichee-Pi-4A board

1. add 'everest,es7210' & 'everest,es8156' dt-bindings
2. add es7210 & es8156 codec driver code
3. add codec node in dts
4. enable codec config

Signed-off-by: David Li <davidli.li@linux.alibaba.com>

Documentation/devicetree/bindings/sound/everest,es7210.txt

+ES7210 i2s DA converter
+
+Required properties:
+- compatible : "everest,es7210" or
+- VDD-supply : regulator phandle for the VDD supply
+- PVDD-supply: regulator phandle for the PVDD supply for the es7210
+
+Example:
+i2s_codec: external-codec {
+	compatible = "everest,es7210";
+	VDD-supply = <&vcc_5v>;
+};

Documentation/devicetree/bindings/sound/everest,es8156.yaml

+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/everest,es8156.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Everest ES8156 audio CODEC
+
+maintainers:
+  - shuofeng.ren <shuofeng.rsf@linux.alibaba.com>
+
+allOf:
+  - $ref: dai-common.yaml#
+
+properties:
+  compatible:
+    const: everest,es8156
+
+  reg:
+    maxItems: 1
+
+  "#sound-dai-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - "#sound-dai-cells"
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    i2c {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      es8156: codec@8 {
+        compatible = "everest,es8156";
+        reg = <0x08>;
+        #sound-dai-cells = <0>;
+      };
+    };

arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts

@@ -668,6 +668,32 @@ aon_log_mem: memory@33600000 {
 
 };
 
+&audio_i2c0 {
+	clock-frequency = <100000>;
+	status = "okay";
+
+	es8156_audio_codec: es8156@8 {
+		#sound-dai-cells = <0>;
+		compatible = "everest,es8156";
+		reg = <0x08>;
+		sound-name-prefix = "ES8156";
+		AVDD-supply = <&reg_aud_3v3>;
+		DVDD-supply = <&reg_aud_1v8>;
+		PVDD-supply = <&reg_aud_1v8>;
+	};
+
+	es7210_audio_codec: es7210@40 {
+		#sound-dai-cells = <0>;
+		compatible = "MicArray_0";
+		reg = <0x40>;
+		sound-name-prefix = "ES7210";
+		MVDD-supply = <&reg_aud_3v3>;
+		AVDD-supply = <&reg_aud_3v3>;
+		DVDD-supply = <&reg_aud_1v8>;
+		PVDD-supply = <&reg_aud_1v8>;
+	};
+};
+
 &light_i2s {
         status = "okay";
 };

arch/riscv/configs/th1520_defconfig

@@ -267,3 +267,6 @@ CONFIG_SND_SOC_XUANTIE=y
 CONFIG_SND_SOC_XUANTIE_TH1520_I2S=y
 # CONFIG_SND_SOC_XUANTIE_TH1520_I2S_CH8 is not set
 CONFIG_SND_SOC_XUANTIE_TH1520_HDMI_PCM=y
+# TH1520 codec
+CONFIG_SND_SOC_ES7210=y
+CONFIG_SND_SOC_ES8156=y

sound/soc/codecs/Kconfig

@@ -106,11 +106,13 @@ config SND_SOC_ALL_CODECS
 	imply SND_SOC_DA732X
 	imply SND_SOC_DA9055
 	imply SND_SOC_DMIC
+	imply SND_SOC_ES8156
 	imply SND_SOC_ES8316
 	imply SND_SOC_ES8326
 	imply SND_SOC_ES8328_SPI
 	imply SND_SOC_ES8328_I2C
 	imply SND_SOC_ES7134
+	imply SND_SOC_ES7210
 	imply SND_SOC_ES7241
 	imply SND_SOC_GTM601
 	imply SND_SOC_HDAC_HDMI
@@ -1047,9 +1049,16 @@ config SND_SOC_HDMI_CODEC
 config SND_SOC_ES7134
 	tristate "Everest Semi ES7134 CODEC"
 
+config SND_SOC_ES7210
+	tristate "Everest Semi ES7210 CODEC"
+
 config SND_SOC_ES7241
 	tristate "Everest Semi ES7241 CODEC"
 
+config SND_SOC_ES8156
+	tristate "Everest Semi ES8156 CODEC"
+	depends on I2C
+
 config SND_SOC_ES8316
 	tristate "Everest Semi ES8316 CODEC"
 	depends on I2C

sound/soc/codecs/Makefile

@@ -113,7 +113,9 @@ snd-soc-da732x-objs := da732x.o
 snd-soc-da9055-objs := da9055.o
 snd-soc-dmic-objs := dmic.o
 snd-soc-es7134-objs := es7134.o
+snd-soc-es7210-objs := es7210.o
 snd-soc-es7241-objs := es7241.o
+snd-soc-es8156-objs := es8156.o
 snd-soc-es8316-objs := es8316.o
 snd-soc-es8326-objs := es8326.o
 snd-soc-es8328-objs := es8328.o
@@ -499,7 +501,9 @@ obj-$(CONFIG_SND_SOC_DA732X)	+= snd-soc-da732x.o
 obj-$(CONFIG_SND_SOC_DA9055)	+= snd-soc-da9055.o
 obj-$(CONFIG_SND_SOC_DMIC)	+= snd-soc-dmic.o
 obj-$(CONFIG_SND_SOC_ES7134)	+= snd-soc-es7134.o
+obj-$(CONFIG_SND_SOC_ES7210)	+= snd-soc-es7210.o
 obj-$(CONFIG_SND_SOC_ES7241)	+= snd-soc-es7241.o
+obj-$(CONFIG_SND_SOC_ES8156)	+= snd-soc-es8156.o
 obj-$(CONFIG_SND_SOC_ES8316)    += snd-soc-es8316.o
 obj-$(CONFIG_SND_SOC_ES8326)    += snd-soc-es8326.o
 obj-$(CONFIG_SND_SOC_ES8328)	+= snd-soc-es8328.o

sound/soc/codecs/es7210.h

+/*
+ * ALSA SoC ES7210 codec driver
+ *
+ * Copyright:   (C) 2018 Everest Semiconductor Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */  
+    
+#ifndef _ES7210_H
+#define _ES7210_H
+    
+#define ES7210_RESET_CTL_REG00		0x00
+#define ES7210_CLK_ON_OFF_REG01		0x01
+#define ES7210_MCLK_CTL_REG02		0x02
+#define ES7210_MST_CLK_CTL_REG03	0x03
+#define ES7210_MST_LRCDIVH_REG04	0x04
+#define ES7210_MST_LRCDIVL_REG05	0x05
+#define ES7210_DIGITAL_PDN_REG06	0x06
+#define ES7210_ADC_OSR_REG07		0x07
+#define ES7210_MODE_CFG_REG08		0x08
+    
+#define ES7210_TCT0_CHPINI_REG09	0x09
+#define ES7210_TCT1_CHPINI_REG0A	0x0A
+#define ES7210_CHIP_STA_REG0B		0x0B
+    
+#define ES7210_IRQ_CTL_REG0C		0x0C
+#define ES7210_MISC_CTL_REG0D		0x0D
+#define ES7210_DMIC_CTL_REG10		0x10
+    
+#define ES7210_SDP_CFG1_REG11		0x11
+#define ES7210_SDP_CFG2_REG12		0x12
+    
+#define ES7210_ADC_AUTOMUTE_REG13	0x13
+#define ES7210_ADC34_MUTE_REG14		0x14
+#define ES7210_ADC12_MUTE_REG15		0x15
+    
+#define ES7210_ALC_SEL_REG16		0x16
+#define ES7210_ALC_COM_CFG1_REG17	0x17
+#define ES7210_ALC34_LVL_REG18		0x18
+#define ES7210_ALC12_LVL_REG19		0x19
+#define ES7210_ALC_COM_CFG2_REG1A	0x1A
+#define ES7210_ALC4_MAX_GAIN_REG1B	0x1B
+#define ES7210_ALC3_MAX_GAIN_REG1C	0x1C
+#define ES7210_ALC2_MAX_GAIN_REG1D	0x1D
+#define ES7210_ALC1_MAX_GAIN_REG1E	0x1E
+    
+#define ES7210_ADC34_HPF2_REG20		0x20
+#define ES7210_ADC34_HPF1_REG21		0x21
+#define ES7210_ADC12_HPF2_REG22		0x22
+#define ES7210_ADC12_HPF1_REG23		0x23
+    
+#define ES7210_CHP_ID1_REG3D		0x3D
+#define ES7210_CHP_ID0_REG3E		0x3E
+#define ES7210_CHP_VER_REG3F		0x3F
+    
+#define ES7210_ANALOG_SYS_REG40		0x40
+    
+#define ES7210_MICBIAS12_REG41		0x41
+#define ES7210_MICBIAS34_REG42		0x42
+#define ES7210_MIC1_GAIN_REG43		0x43
+#define ES7210_MIC2_GAIN_REG44		0x44
+#define ES7210_MIC3_GAIN_REG45		0x45
+#define ES7210_MIC4_GAIN_REG46		0x46
+#define ES7210_MIC1_LP_REG47		0x47
+#define ES7210_MIC2_LP_REG48		0x48
+#define ES7210_MIC3_LP_REG49		0x49
+#define ES7210_MIC4_LP_REG4A		0x4A
+#define ES7210_MIC12_PDN_REG4B		0x4B
+#define ES7210_MIC34_PDN_REG4C		0x4C
+
+/* codec private data */
+struct es7210_priv {
+        struct regmap *regmap;
+        struct i2c_client *i2c_client;
+        unsigned int dmic_enable;
+        unsigned int sysclk;
+        struct clk *mclk;
+        struct snd_pcm_hw_constraint_list *sysclk_constraints;
+        struct regulator *mvdd;
+        struct regulator *avdd;
+        struct regulator *dvdd;
+        struct regulator *pvdd;
+        unsigned int tdm_mode;
+        struct delayed_work pcm_pop_work;
+        int mclk_lrck_ratio;
+        int pcm_format;
+        int mclk_sclk_ratio; // mclk_sclk_ratio=1 is when mclk hardwired to sclk.
+        int sclk_lrck_ratio;
+
+        u8 suspend_reg00[4];
+        u8 suspend_reg01[4];
+        u8 suspend_reg02[4];
+        u8 suspend_reg03[4];
+        u8 suspend_reg04[4];
+        u8 suspend_reg05[4];
+        u8 suspend_reg06[4];
+        u8 suspend_reg07[4];
+        u8 suspend_reg08[4];
+        u8 suspend_reg09[4];
+        u8 suspend_reg0A[4];
+        u8 suspend_reg0B[4];
+        u8 suspend_reg0C[4];
+        u8 suspend_reg0D[4];
+        u8 suspend_reg10[4];
+        u8 suspend_reg11[4];
+        u8 suspend_reg12[4];
+        u8 suspend_reg13[4];
+        u8 suspend_reg14[4];
+        u8 suspend_reg15[4];
+        u8 suspend_reg16[4];
+        u8 suspend_reg17[4];
+        u8 suspend_reg18[4];
+        u8 suspend_reg19[4];
+        u8 suspend_reg1A[4];
+        u8 suspend_reg1B[4];
+        u8 suspend_reg1C[4];
+        u8 suspend_reg1D[4];
+        u8 suspend_reg1E[4];
+        u8 suspend_reg20[4];
+        u8 suspend_reg21[4];
+        u8 suspend_reg22[4];
+        u8 suspend_reg23[4];
+        u8 suspend_reg40[4];
+        u8 suspend_reg41[4];
+        u8 suspend_reg42[4];
+        u8 suspend_reg43[4];
+        u8 suspend_reg44[4];
+        u8 suspend_reg45[4];
+        u8 suspend_reg46[4];
+        u8 suspend_reg47[4];
+        u8 suspend_reg48[4];
+        u8 suspend_reg49[4];
+        u8 suspend_reg4A[4];
+        u8 suspend_reg4B[4];
+        u8 suspend_reg4C[4];
+};
+
+#endif	/* _ES7210_H_ */

sound/soc/codecs/es8156.h

+/*
+ * Copyright Everest Semiconductor Co.,Ltd *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ES8156_H
+#define _ES8156_H
+
+/* ES8156 register space */
+/*
+* RESET Control
+*/
+#define ES8156_RESET_REG00             0x00
+/*
+* Clock Managerment
+*/
+#define ES8156_MAINCLOCK_CTL_REG01     0x01
+#define ES8156_SCLK_MODE_REG02     		 0x02
+#define ES8156_LRCLK_DIV_H_REG03     0x03
+#define ES8156_LRCLK_DIV_L_REG04    0x04
+#define ES8156_SCLK_DIV_REG05    0x05
+#define ES8156_NFS_CONFIG_REG06    0x06
+#define ES8156_MISC_CONTROL1_REG07    0x07
+#define ES8156_CLOCK_ON_OFF_REG08      0x08
+#define ES8156_MISC_CONTROL2_REG09     0x09
+#define ES8156_TIME_CONTROL1_REG0A        0x0a
+#define ES8156_TIME_CONTROL2_REG0B        0x0b
+/*
+* System Control
+*/
+#define ES8156_CHIP_STATUS_REG0C       0x0c
+#define ES8156_P2S_CONTROL_REG0D           0x0d
+#define ES8156_DAC_OSR_COUNTER_REG10       0x10
+/*
+* SDP Control
+*/
+#define ES8156_DAC_SDP_REG11          0x11
+#define ES8156_AUTOMUTE_SET_REG12           0x12
+#define ES8156_DAC_MUTE_REG13         0x13
+#define ES8156_VOLUME_CONTROL_REG14      0x14
+
+/*
+* ALC Control
+*/
+#define ES8156_ALC_CONFIG1_REG15         0x15
+#define ES8156_ALC_CONFIG2_REG16         0x16
+#define ES8156_ALC_CONFIG3_REG17        0x17
+#define ES8156_MISC_CONTROL3_REG18     0x18
+#define ES8156_EQ_CONTROL1_REG19         0x19
+#define ES8156_EQ_CONTROL2_REG1A         0x1a
+/*
+* Analog System Control
+*/
+#define ES8156_ANALOG_SYS1_REG20        0x20
+#define ES8156_ANALOG_SYS2_REG21        0x21
+#define ES8156_ANALOG_SYS3_REG22   0x22
+#define ES8156_ANALOG_SYS4_REG23      0x23
+#define ES8156_ANALOG_LP_REG24      0x24
+#define ES8156_ANALOG_SYS5_REG25         0x25
+/*
+* Chip Information
+*/
+#define ES8156_I2C_PAGESEL_REGFC         0xFC
+#define ES8156_CHIPID1_REGFD       0xFD
+#define ES8156_CHIPID0_REGFE        0xFE
+#define ES8156_CHIP_VERSION_REGFF         0xFF
+
+
+enum vmidlow {
+	VMIDLEVEL0,
+	VMIDLEVEL1,
+	VMIDLEVEL2,
+    VMIDLEVEL3,
+};
+
+#define ES8156_3V3 0
+#define ES8156_1V8 1
+#define ES8156_DVDD ES8156_1V8
+
+#endif
+