KVM: MMU: Add 5 level EPT & Shadow page table support.
Extends the shadow paging code, so that 5 level shadow page table can be constructed if VM is running in 5 level paging mode. Also extends the ept code, so that 5 level ept table can be constructed if maxphysaddr of VM exceeds 48 bits. Unlike the shadow logic, KVM should still use 4 level ept table for a VM whose physical address width is less than 48 bits, even when the VM is running in 5 level paging mode. Signed-off-by:Yu Zhang <yu.c.zhang@linux.intel.com> [Unconditionally reset the MMU context in kvm_cpuid_update. Changing MAXPHYADDR invalidates the reserved bit bitmasks. - Paolo] Signed-off-by:
Paolo Bonzini <pbonzini@redhat.com>
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- arch/x86/include/asm/kvm_host.h 5 additions, 5 deletionsarch/x86/include/asm/kvm_host.h
- arch/x86/include/asm/vmx.h 2 additions, 0 deletionsarch/x86/include/asm/vmx.h
- arch/x86/kvm/cpuid.c 1 addition, 0 deletionsarch/x86/kvm/cpuid.c
- arch/x86/kvm/mmu.c 29 additions, 14 deletionsarch/x86/kvm/mmu.c
- arch/x86/kvm/mmu.h 1 addition, 0 deletionsarch/x86/kvm/mmu.h
- arch/x86/kvm/mmu_audit.c 2 additions, 2 deletionsarch/x86/kvm/mmu_audit.c
- arch/x86/kvm/svm.c 2 additions, 2 deletionsarch/x86/kvm/svm.c
- arch/x86/kvm/vmx.c 15 additions, 6 deletionsarch/x86/kvm/vmx.c
- arch/x86/kvm/x86.h 10 additions, 0 deletionsarch/x86/kvm/x86.h
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