- Oct 31, 2016
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Giovanni Cabiddu authored
Fix dependency between acomp and scomp that appears when acomp is built as module Signed-off-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
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Arnd Bergmann authored
Building the caam driver on arm64 produces a harmless warning: drivers/crypto/caam/caamalg.c:140:139: warning: comparison of distinct pointer types lacks a cast We can use min_t to tell the compiler which type we want it to use here. Fixes: 5ecf8ef9 ("crypto: caam - fix sg dump") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Reviewed-by:
Horia Geantă <horia.geanta@nxp.com> Signed-off-by:
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Colin Ian King authored
Trivial fix to typo in dev_dbg message Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Wei Yongjun authored
There is no need to have the 'struct atmel_aes_dev *aes_dd' variable static since new value always be assigned before use it. Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
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Stephan Mueller authored
The HWRNG core allocates two buffers during initialization which are used to obtain random data. After that data is processed, it is now zeroized as it is possible that the HWRNG core will not be asked to produce more random data for a long time. This prevents leaving such sensitive data in memory. Signed-off-by:
Stephan Mueller <smueller@chronox.de> Signed-off-by:
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- Oct 24, 2016
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Giovanni Cabiddu authored
Add tests to the test manager for algorithms exposed through acomp. Signed-off-by:
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Giovanni Cabiddu authored
Add scomp backend for deflate compression algorithm. Signed-off-by:
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Giovanni Cabiddu authored
Add scomp backend for 842 compression algorithm. Signed-off-by:
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Giovanni Cabiddu authored
Add scomp backend for lz4hc compression algorithm. Signed-off-by:
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Giovanni Cabiddu authored
Add scomp backend for lz4 compression algorithm. Signed-off-by:
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Giovanni Cabiddu authored
Add scomp backend for lzo compression algorithm. Signed-off-by:
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Giovanni Cabiddu authored
Add a synchronous back-end (scomp) to acomp. This allows to easily expose the already present compression algorithms in LKCF via acomp. Signed-off-by:
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Giovanni Cabiddu authored
Add acomp, an asynchronous compression api that uses scatterlist buffers. Signed-off-by:
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Paul Bolle authored
The abbreviation for Cryptographic Coprocessor is "CCP". Signed-off-by:
Paul Bolle <pebolle@tiscali.nl> Acked-by:
Gary R Hook <gary.hook@amd.com> Signed-off-by:
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Javier Martinez Canillas authored
The Amlogic Meson is a DT-only platform, which means the devices are registered via OF and not using the legacy platform devices support. So there's no need to have a MODULE_ALIAS("platform:meson-rng") since the reported uevent MODALIAS to user-space will always be the OF one. Signed-off-by:Javier Martinez Canillas <javier@osg.samsung.com> Acked-by:
Kevin Hilman <khilman@baylibre.com> Acked-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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Petr Mladek authored
Use the new API to create and destroy the crypto engine kthread worker. The API hides some implementation details. In particular, kthread_create_worker() allocates and initializes struct kthread_worker. It runs the kthread the right way and stores task_struct into the worker structure. kthread_destroy_worker() flushes all pending works, stops the kthread and frees the structure. This patch does not change the existing behavior except for dynamically allocating struct kthread_worker and storing only the pointer of this structure. It is compile tested only because I did not find an easy way how to run the code. Well, it should be pretty safe given the nature of the change. Signed-off-by:
Petr Mladek <pmladek@suse.com> Signed-off-by:
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Gary R Hook authored
Fix a few problems revealed by testing: verify consistent units, especially in public slot allocation. Percolate some common initialization code up to a common routine. Add some comments. Signed-off-by:
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Gary R Hook authored
Clean up patch for an unneeded structure member. Signed-off-by:
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Gary R Hook authored
Bit fields are not sensitive to endianness, so use a transparent standard data type Signed-off-by:
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Javier Martinez Canillas authored
If the driver is built as a module, autoload won't work because the module alias information is not filled. So user-space can't match the registered device with the corresponding module. Export the module alias information using the MODULE_DEVICE_TABLE() macro. Before this patch: $ modinfo drivers/char/hw_random/meson-rng.ko | grep alias alias: platform:meson-rng After this patch: $ modinfo drivers/char/hw_random/meson-rng.ko | grep alias alias: platform:meson-rng alias: of:N*T*Camlogic,meson-rngC* alias: of:N*T*Camlogic,meson-rng Signed-off-by:
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Wei Yongjun authored
Fix to return error code -EINVAL from the invalid alg ivsize error handling case instead of 0, as done elsewhere in this function. Signed-off-by:
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Wei Yongjun authored
Fixes the following sparse warning: drivers/crypto/ccp/ccp-dev.c:44:6: warning: symbol 'ccp_error_codes' was not declared. Should it be static? Signed-off-by:
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Marcus Folkesson authored
i.MX6UL does only require three clocks to enable CAAM module. Signed-off-by:
Marcus Folkesson <marcus.folkesson@gmail.com> Acked-by:
Rob Herring <robh@kernel.org> Reviewed-by:
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Tobias Klauser authored
Remove the unused but set variable pinst in padata_parallel_worker to fix the following warning when building with 'W=1': kernel/padata.c: In function ‘padata_parallel_worker’: kernel/padata.c:68:26: warning: variable ‘pinst’ set but not used [-Wunused-but-set-variable] Also remove the now unused variable pd which is only used to set pinst. Signed-off-by:
Tobias Klauser <tklauser@distanz.ch> Acked-by:
Steffen Klassert <steffen.klassert@secunet.com> Signed-off-by:
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- Oct 20, 2016
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Gary R Hook authored
The lsb field uses a value of -1 to indicate that it is unassigned. Therefore type must be a signed int. Signed-off-by:
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Ard Biesheuvel authored
The AES key schedule generation is mostly endian agnostic, with the exception of the rotation and the incorporation of the round constant at the start of each round. So implement a big endian specific version of that part to make the whole routine big endian compatible. Fixes: 86464859 ("crypto: arm - AES in ECB/CBC/CTR/XTS modes using ARMv8 Crypto Extensions") Signed-off-by:
Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by:
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Ard Biesheuvel authored
Emit the XTS tweak literal constants in the appropriate order for a single 128-bit scalar literal load. Fixes: 49788fe2 ("arm64/crypto: AES-ECB/CBC/CTR/XTS using ARMv8 NEON and Crypto Extensions") Signed-off-by:
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Ard Biesheuvel authored
The AES implementation using pure NEON instructions relies on the generic AES key schedule generation routines, which store the round keys as arrays of 32-bit quantities stored in memory using native endianness. This means we should refer to these round keys using 4x4 loads rather than 16x1 loads. In addition, the ShiftRows tables are loading using a single scalar load, which is also affected by endianness, so emit these tables in the correct order depending on whether we are building for big endian or not. Fixes: 49788fe2 ("arm64/crypto: AES-ECB/CBC/CTR/XTS using ARMv8 NEON and Crypto Extensions") Signed-off-by:
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Ard Biesheuvel authored
The AES-CCM implementation that uses ARMv8 Crypto Extensions instructions refers to the AES round keys as pairs of 64-bit quantities, which causes failures when building the code for big endian. In addition, it byte swaps the input counter unconditionally, while this is only required for little endian builds. So fix both issues. Fixes: 12ac3efe ("arm64/crypto: use crypto instructions to generate AES key schedule") Signed-off-by:
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Ard Biesheuvel authored
The SHA256 digest is an array of 8 32-bit quantities, so we should refer to them as such in order for this code to work correctly when built for big endian. So replace 16 byte scalar loads and stores with 4x32 vector ones where appropriate. Fixes: 6ba6c74d ("arm64/crypto: SHA-224/SHA-256 using ARMv8 Crypto Extensions") Signed-off-by:
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Ard Biesheuvel authored
The SHA1 digest is an array of 5 32-bit quantities, so we should refer to them as such in order for this code to work correctly when built for big endian. So replace 16 byte scalar loads and stores with 4x4 vector ones where appropriate. Fixes: 2c98833a ("arm64/crypto: SHA-1 using ARMv8 Crypto Extensions") Signed-off-by:
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Ard Biesheuvel authored
The GHASH key and digest are both pairs of 64-bit quantities, but the GHASH code does not always refer to them as such, causing failures when built for big endian. So replace the 16x1 loads and stores with 2x8 ones. Fixes: b913a640 ("arm64/crypto: improve performance of GHASH algorithm") Signed-off-by:
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Ard Biesheuvel authored
The core AES cipher implementation that uses ARMv8 Crypto Extensions instructions erroneously loads the round keys as 64-bit quantities, which causes the algorithm to fail when built for big endian. In addition, the key schedule generation routine fails to take endianness into account as well, when loading the combining the input key with the round constants. So fix both issues. Fixes: 12ac3efe ("arm64/crypto: use crypto instructions to generate AES key schedule") Signed-off-by:
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Eric Biggers authored
The per-transform 'consts' array is accessed as __be64 in crypto_cmac_digest_setkey() but was only guaranteed to be aligned to __alignof__(long). Fix this by aligning it to __alignof__(__be64). Signed-off-by:
Eric Biggers <ebiggers@google.com> Signed-off-by:
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Eric Biggers authored
cmac_create() previously returned 0 if a cipher with a block size other than 8 or 16 bytes was specified. It should return -EINVAL instead. Granted, this doesn't actually change any behavior because cryptomgr currently ignores any return value other than -EAGAIN from template ->create() functions. Signed-off-by:
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Eric Biggers authored
crypto_exit_cipher_ops() and crypto_exit_compress_ops() are no-ops and have been for a long time, so remove them. Signed-off-by:
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Eric Biggers authored
The definition of crypto_lookup_skcipher() was already removed in commit 3a01d0ee ("crypto: skcipher - Remove top-level givcipher interface"). So the declaration should be removed too. Signed-off-by:
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Christophe Jaillet authored
The size used in 'dma_free_coherent()' looks un-initialized here. ctx->sa_len is set a few lines below and is apparently not set by the caller. So use 'size' as in the corresponding 'dma_alloc_coherent()' a few lines above. This has been spotted with coccinelle, using the following script: //////////////////// @r@ expression x0, x1, y0, y1, z0, z1, t0, t1, ret; @@ * ret = dma_alloc_coherent(x0, y0, z0, t0); ... * dma_free_coherent(x1, y1, ret, t1); @script:python@ y0 << r.y0; y1 << r.y1; @@ if y1.find(y0) == -1: print "WARNING: sizes look different: '%s' vs '%s'" % (y0, y1) //////////////////// Signed-off-by:Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Romain Perier authored
Currently, the driver breaks chain for all kind of hash requests in order to don't override intermediate states of partial ahash updates. However, some final ahash requests can be directly processed by the engine, and so without intermediate state. This is typically the case for most for the HMAC requests processed via IPSec. This commits adds a TDMA descriptor to copy context for these of requests into the "op" dma pool, then it allow to chain these requests at the DMA level. The 'complete' operation is also updated to retrieve the MAC digest from the right location. Signed-off-by:
Romain Perier <romain.perier@free-electrons.com> Acked-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by:
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Romain Perier authored
So far, we used a dedicated dma pool to copy the result of outer IV for cipher requests. Instead of using a dma pool per outer data, we prefer use the op dma pool that contains all part of the request from the SRAM. Then, the outer data that is likely to be used by the 'complete' operation, is copied later. In this way, any type of result can be retrieved by DMA for cipher or ahash requests. Signed-off-by:
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