Merge remote-tracking branch 'upstream/main' into main

a8121a67 · Jason Kridner · cf8301d7 · a31adbb1 · a8121a67 · a8121a67
Commit a8121a67 authored 2 years ago by Jason Kridner
--- a/VERSION
+++ b/VERSION
 VERSION_MAJOR = 0
 VERSION_MINOR = 0
 PATCHLEVEL = 5
-VERSION_TWEAK = 2
+VERSION_TWEAK = 3
 EXTRAVERSION = beta
--- a/_static/css/custom.css
+++ b/_static/css/custom.css
@@ -17,8 +17,10 @@
    max-width: 480px;
 }

-.wy-nav-content {
-    max-width: 100%;
+@media only screen and (min-width: 769px) {
+    .wy-nav-content {
+        max-width: 915px;
+    }
 }

 .wy-side-nav-search {
@@ -34,4 +36,39 @@
 .wy-nav-side {
    background-color: #25282b;
    background-color: #25282b;
+}
+
+/* Table display tweaks */
+
+.rst-content table.docutils,
+.wy-table-bordered-all td,
+.rst-content table.docutils td,
+.wy-table thead th,
+.rst-content table.docutils thead th,
+.rst-content table.field-list thead th {
+    border-color: var(--code-border-color);
+}
+
+.wy-table-odd td,
+.wy-table-striped tr:nth-child(2n-1) td,
+.rst-content table.docutils:not(.field-list) tr:nth-child(2n-1) td {
+    background-color: var(--table-row-odd-background-color);
+}
+
+/* Override table no-wrap */
+/* The first column cells are not verbose, no need to wrap them */
+.wy-table-responsive table td:not(:nth-child(1)),
+.wy-table-responsive table th:not(:nth-child(1)) {
+    white-space: normal;
+}
+
+/* Make sure not to wrap keyboard shortcuts */
+.wy-table-responsive table td kbd {
+    white-space: nowrap;
+}
+
+/* Force table content font-size in responsive tables to be 100%
+ * fixing larger font size for paragraphs in the kconfig tables */
+ .wy-table-responsive td p {
+    font-size: 100%;
 }
\ No newline at end of file
--- a/_static/latex/preamble.tex
+++ b/_static/latex/preamble.tex
@@ -5,6 +5,8 @@

 \usepackage[some]{background}
 \usepackage{sectsty}
+\usepackage{lscape}
+\usepackage{longtable}

 \definecolor{bg-color}{HTML}{a97f2c}


--- a/beaglebone-ai-64/ch06.rst
+++ b/beaglebone-ai-64/ch06.rst
+:orphan:
+
 .. _detailed-hardware-design:

 Detailed Hardware Design

--- a/beaglebone-ai-64/ch07.rst
+++ b/beaglebone-ai-64/ch07.rst
+:orphan:
+
 .. _connectors:

 Connectors

--- a/beaglebone-ai-64/ch08.rst
+++ b/beaglebone-ai-64/ch08.rst
+:orphan:
+
 .. _cape-board-support-1:

 Cape Board Support

--- a/beaglebone-black/System-Reference-Manual.asciidoc
+++ b/beaglebone-black/System-Reference-Manual.asciidoc
@@ -11,10 +11,10 @@
 image:media/image1.jpg[media/image1.jpg,title="media/image1.jpg",width=598,height=400,align="center"]

 [.text-center]
-*Revision C.2 (wiki to PDF snapshot)*
+*Revision C.3 (wiki to PDF snapshot)*

 [.text-center]
-*Last PDF conversion: May 6, 2020*
+*Last PDF conversion: August 24, 2021*

 ______________________________________________________________________________________________________________________________________________________
 *Maintaining editor: Jason Kridner* _jkridner@beagleboard.org_
@@ -271,6 +271,7 @@ https://elinux.org/Beagleboard:BeagleBoneBlack

 [[change-history]]
 == 2.0 Change History
+
 This section describes the change history of this document and board.
 Document changes are not always a result of a board change. A board
 change will always result in a document change.
@@ -319,13 +320,51 @@ pin. +
 2. Added additional supplier to DDR2 and eMMC. |March 21,2014 |GC
 |C.1 |1. Added note to recommend powering off the board with the power |March 22, 2014 |GC
 |C.2 |Numerous community edits and format changes to asciidoc. |May 6, 2020 |JK
+|C.3 |Added information for board rev C3. |August 24, 2021 |JK
 |=======================================================================

 [[board-changes]]
 === 2.2 Board Changes

+[[rev-c3]]
+==== 2.2.1 Rev C3
+
+PCB revision C.
+
+* Updated microSD card cage due to availability. See https://github.com/beagleboard/beaglebone-black/issues/6. Added series resistors and depopulated C5.
+* Added reset option (GPIO1_8) for Ethernet PHY to avoid possible start-up issue. See https://github.com/beagleboard/beaglebone-black/issues/4.
+* Added series resistors to MMC1 lines and depopulated C24.
+* Connected pin A6 of J5 on U13 (eMMC IC) to DGND.
+* Changed USB1_VBUS series resistor to 0 ohm.
+* Change required PCB revision to C.
+
+Initial boxes mistakenly say rev C1.
+
+[[rev-c2]]
+==== 2.2.2 Rev C2
+
+PCB revision B6.
+
+* Update memories based on availability. See https://github.com/beagleboard/beaglebone-black/commit/74914bd01efeb61376ec3dda4bf9143ad2bb635c.
+** DDR3:
+*** Kingston D2516EC4BXGGB-U
+** eMMC:
+**** Kingston MMC04G-M627-X02U
+
+[[rev-c1]]
+==== 2.2.3 Rev C1
+
+PCB revision B6.
+
+* Update memories based on availability. See https://github.com/beagleboard/beaglebone-black/commit/5787736d816832cc8cc9629d19f334b6a12e67f9.
+** DDR3:
+*** Micron MT41K256M16TW-107:P
+** eMMC:
+*** Micron MTFC4GACAJCN-1M WT
+*** Kingston EMMC04G-S100-A08U
+
 [[rev-c]]
-==== 2.2.1 Rev C
+==== 2.2.4 Rev C

 * Changed the eMMC from 2GB to 4GB.

@@ -334,12 +373,12 @@ required us to move to 4GB. We now have two sources for the device. This
 will however, require an increase in the price of the board.

 [[rev-b]]
-==== 2.2.2 Rev B
+==== 2.2.5 Rev B

 * Changed the processor to the AM3358BZCZ100.

 [[rev-a6a]]
-==== 2.2.3 Rev A6A
+==== 2.2.6 Rev A6A

 * Added connection from 32KHz OSC_GND to system ground and changed C106
 to 1uF.
@@ -348,7 +387,7 @@ boards where the board would not boot in 1 in 20 tries.
 * Change required PCB revision to B6.

 [[rev-a6]]
-==== 2.2.4 Rev A6
+==== 2.2.7 Rev A6

 * In random instances there could be a glitch in the SYS_RESETn signal
 from the processor where the SYS_RESETn signal was taken high for a
@@ -361,7 +400,7 @@ resistor was added to connect the OSC_GND to the system ground.
 There are no new features added as a result of these changes.

 [[rev-a5c]]
-==== 2.2.5 Rev A5C
+==== 2.2.8 Rev A5C

 We were seeing some fallout in production test where we were seeing some
 jitter on the HDMI display test. It started showing up on out second
@@ -373,7 +412,7 @@ issue was caught in production test. No impact on features or
 functionality resulted from this change.

 [[rev-a5b]]
-==== 2.2.6 Rev A5B
+==== 2.2.9 Rev A5B

 There is no operational difference between the Rev A5A and the Rev A5B.
 There were two changes made to the A5B version.
@@ -390,7 +429,7 @@ was not a result of any hardware changes but only updated software. The
 A5A version also supports this resolution.

 [[rev-a5a]]
-==== 2.2.7 Rev A5A
+==== 2.2.10 Rev A5A

 This is the initial production release of the board. We will be tracking
 changes from this point forward.
@@ -988,7 +1027,7 @@ warm reset only and will not force a boot mode_ _change._
 === 5.4 Power Management

 The *TPS65217C* power management device is used along with a separate
-LDO to provide power to the system. The**TPS65217C** version provides
+LDO to provide power to the system. The **TPS65217C** version provides
 for the proper voltages required for the DDR3L. This is the same device
 as used on the original BeagleBone with the exception of the power rail
 configuration settings which will be changed in the internal EEPROM to
@@ -1266,7 +1305,7 @@ limited to 500mA max. When powering from the USB port, the VDD_5V rail
 is not provided to the expansion headers, so capes that require the 5V
 rail to supply the cape direct, bypassing the *TPS65217C*, will not have
 that rail available for use. The 5VDC supply from the USB port is
-provided on the SYS_5V, the one that comes from the**TPS65217C**, rail
+provided on the SYS_5V, the one that comes from the **TPS65217C**, rail
 of the expansion header for use by a cape. *Figure 24* is the connection
 of the USB power input on the PMIC.

@@ -1281,7 +1320,7 @@ The selection of either the 5VDC or the USB as the power source is
 handled internally to the *TPS65217C* and automatically switches to 5VDC
 power if both are connected. SW can change the power configuration via
 the I2C interface from the processor. In addition, the SW can read
-the**TPS65217C** and determine if the board is running on the 5VDC input
+the **TPS65217C** and determine if the board is running on the 5VDC input
 or the USB input. This can be beneficial to know the capability of the
 board to supply current for things like operating frequency and
 expansion cards.
@@ -1298,7 +1337,7 @@ momentary switch, the same type of switch used for reset and boot
 selection on the board.

 If you push the button the *TPS65217C* will send an interrupt to the
-processor. It is up to the processor to then pull the**PMIC_POWER_EN**
+processor. It is up to the processor to then pull the **PMIC_POWER_EN**
 pin low at the correct time to power down the board. At this point, the
 PMIC is still active, assuming that the power input was not removed.
 Pressing the power button will cause the board to power up again if the
@@ -1391,14 +1430,14 @@ signals. Each of these signals is described below.
 ===== 6.1.8.1 I2C0

 I2C0 is the control interface between the processor and the *TPS65217C*.
-It allows the processor to control the registers inside the**TPS65217C**
+It allows the processor to control the registers inside the **TPS65217C**
 for such things as voltage scaling and switching of the input rails.

 [[pmc_powr_en]]
 ===== 6.1.8.2 PMIC_POWR_EN

 On power up the *VDD_RTC* rail activates first. After the RTC circuitry
-in the processor has activated it instructs the**TPS65217C** to initiate
+in the processor has activated it instructs the **TPS65217C** to initiate
 a full power up cycle by activating the *PMIC_POWR_EN* signal by taking
 it HI. When powering down, the processor can take this pin low to start
 the power down process.
@@ -1408,7 +1447,7 @@ the power down process.

 This signal connects to the *RTC_PORZn* signal, RTC power on reset. The
 small “*n*” indicates that the signal is an active low signal. Word
-processors seem to be unable to put a bar over a word so the**n** is
+processors seem to be unable to put a bar over a word so the **n** is
 commonly used in electronics. As the RTC circuitry comes up first, this
 signal indicates that the LDOs, the 1.8V VRTC rail, is up and stable.
 This starts the power up process.
@@ -1417,13 +1456,13 @@ This starts the power up process.
 ===== 6.1.8.4 PMIC_PGOOD

 Once all the rails are up, the *PMIC_PGOOD* signal goes high. This
-releases the**PORZn** signal on the processor which was holding the
+releases the **PORZn** signal on the processor which was holding the
 processor reset.

 [[wakeup]]
 ===== 6.1.8.5 WAKEUP

-The WAKEUP signal from the *TPS65217C* is connected to the**EXT_WAKEUP**
+The WAKEUP signal from the *TPS65217C* is connected to the **EXT_WAKEUP**
 signal on the processor. This is used to wake up the processor when it
 is in a sleep mode. When an event is detected by the *TPS65217C*, such
 as the power button being pressed, it generates this signal.
@@ -1463,7 +1502,7 @@ The *VDD_3V3A* rail is supplied by the **TPS65217C** and provides the

 The current supplied by the *VDD_3V3A* rail is not sufficient to power
 all of the 3.3V rails on the board. So a second LDO is supplied, U4,
-a**TL5209A**, which sources the *VDD_3V3B* rail. It is powered up just
+a **TL5209A**, which sources the *VDD_3V3B* rail. It is powered up just
 after the *VDD_3V3A* rail.

 ===== 6.1.9.4 VDD_1V8 Rail
@@ -1507,7 +1546,7 @@ Instruments.
 .Figure 26. Power Rail Power Up Sequencing
 image:media/image40.png[media/image40.png,title="media/image40.png",width=547,height=397]

-<<figure-27>> the voltage rail sequencing for the**TPS65217C** as it
+<<figure-27>> the voltage rail sequencing for the **TPS65217C** as it
 powers up and the voltages on each rail. The power sequencing starts at
 15 and then goes to one. That is the way the *TPS65217C* is configured.
 You can refer to the TPS65217C datasheet for more information.
@@ -1521,7 +1560,7 @@ image:media/image41.png[media/image41.png,title="media/image41.png",width=225,he

 The power LED is a blue LED that will turn on once the *TPS65217C* has
 finished the power up procedure. If you ever see the LED flash once,
-that means that the**TPS65217C** started the process and encountered an
+that means that the **TPS65217C** started the process and encountered an
 issue that caused it to shut down. The connection of the LED is shown in
 <<figure-25>>.

@@ -1549,11 +1588,11 @@ processor is released.

 Once the *RTC_PORZn* reset is released, the processor starts the
 initialization process. After the RTC stabilizes, the processor launches
-the rest of the power up process by activating the**PMIC_POWER_EN**
+the rest of the power up process by activating the **PMIC_POWER_EN**
 signal that is connected to the *TPS65217C* which starts the *TPS65217C*
 power up process.

-The *LDO_PGOOD* signal is provided by the**TPS65217C** to the processor.
+The *LDO_PGOOD* signal is provided by the **TPS65217C** to the processor.
 As this signal is 1.8V from the *TPS65217C* by virtue of the *TPS65217C*
 VIO rail being set to 1.8V, and the *RTC_PORZ* signal on the processor
 is 3.3V, a voltage level shifter, *U4*, is used. Once the LDOs and
@@ -1565,7 +1604,7 @@ rail on the processor.
 ==== 6.1.12 Processor Control Interface

 <<figure-28>> above shows two interfaces between the processor and
-the**TPS65217C** used for control after the power up sequence has
+the **TPS65217C** used for control after the power up sequence has
 completed.

 The first is the *I2C0* bus. This allows the processor to turn on and
@@ -1588,13 +1627,13 @@ to the HW design.

 In this mode all rails are turned off except the *VDD_RTC*. The
 processor will need to turn off all the rails to enter this mode.
-The**VDD_RTC** staying on will keep the RTC active and provide for the
+The **VDD_RTC** staying on will keep the RTC active and provide for the
 wakeup interfaces to be active to respond to a wake up event.

 ===== 6.1.13.2 RTC Plus DDR

 In this mode all rails are turned off except the *VDD_RTC* and
-the**VDDS_DDR**, which powers the DDR3L memory. The processor will need
+the **VDDS_DDR**, which powers the DDR3L memory. The processor will need
 to turn off all the rails to enter this mode. The *VDD_RTC* staying on
 will keep the RTC active and provide for the wakeup interfaces to be
 active to respond to a wake up event.
@@ -1809,13 +1848,13 @@ LOAD MODE command. ODT is referenced to VREFCA.
 ==== 6.2.8 Power Rails

 The *DDR3L* memory device and the DDR3 rails on the processor are
-supplied by the**TPS65217C**. Default voltage is 1.5V but can be scaled
+supplied by the **TPS65217C**. Default voltage is 1.5V but can be scaled
 down to 1.35V if desired.

 [[vref]]
 ==== 6.2.9 VREF

-The *VREF* signal is generated from a voltage divider on the**VDDS_DDR**
+The *VREF* signal is generated from a voltage divider on the **VDDS_DDR**
 rail that powers the processor DDR rail and the DDR3L device itself.
 *Figure 33* below shows the configuration of this signal and the
 connection to the DDR3L memory device and the processor.
@@ -1986,7 +2025,7 @@ sent.
 There is no separate card detect pin in the microSD specification. It
 uses *MMCO_DAT3* for that function. However, most microSD connectors
 still supply a CD function on the connectors. In the BeagleBone Black
-design, this pin is connected to the**MMC0_SDCD** pin for use by the
+design, this pin is connected to the **MMC0_SDCD** pin for use by the
 processor. You can also change the pin to *GPIO0_6*, which is able to
 wake up the processor from a sleep mode when an microSD card is inserted
 into the connector.
@@ -2139,7 +2178,7 @@ The VDD_3V3B rail is the main power rail for the *LAN8710A*. It
 originates at the VD_3V3B regulator and is the primary rail that
 supports all of the peripherals on the board. This rail also supplies
 the VDDIO rails which set the voltage levels for all of the I/O signals
-between the processor and the**LAN8710A**.
+between the processor and the **LAN8710A**.

 ===== 6.9.3.2 VDD_PHYA Rail

@@ -2259,7 +2298,7 @@ The *Figure 44* shows the connections between the processor and the HDMI
 framer device. There are 16 bits of display data, 5-6-5 that is used to
 drive the framer. The reason for 16 bits is that allows for
 compatibility with display and LCD capes already available on the
-original BeagleBone. The unused bits on the**TDA19988** are tied low. In
+original BeagleBone. The unused bits on the **TDA19988** are tied low. In
 addition to the data signals are the VSYNC, HSYNC, DE, and PCLK signals
 that round out the video interface from the processor.

@@ -2363,7 +2402,7 @@ image:media/image66.png[media/image66.png,title="media/image66.png",width=570,he

 *U8* is a switch that allows the power to the connector to be turned on
 or off by the processor. It also has an over current detection that can
-alert the processor if the current gets too high via the**USB1_OC**
+alert the processor if the current gets too high via the **USB1_OC**
 signal. The power is controlled by the *USB1_DRVBUS* signal from the
 processor.

@@ -4650,7 +4689,7 @@ the operation of these pins if used for other functions.
 framer being powered through these input pins which would not a be a
 good idea.
 * These pins are also the *SYSBOOT* pins. DO NOT drive them before
-the**SYS_RESETN** signal goes high. If you do, the board may not boot
+the **SYS_RESETN** signal goes high. If you do, the board may not boot
 because you would be changing the boot order of the processor.

 In order to use these pins, the SW will need to reconfigure them to

--- a/beaglebone-black/ch01.rst
+++ b/beaglebone-black/ch01.rst
-.. _bbb-introduction:
+.. _beagleboneblack-introduction:

 Introduction
 #################
@@ -18,9 +18,7 @@ experience. Software updates will be frequent and will be independent of
 the hardware revisions and as such not result in a change in the
 revision number.

-Make sure you check the support Wikis frequently for the most up to date
+Make sure you check the docs repository frequently for the most up to date
 information.

-https://github.com/beagleboard/beaglebone-black/wiki
-
-https://elinux.org/Beagleboard:BeagleBoneBlack
+https://git.beagleboard.org/docs/docs.beagleboard.io/-/tree/main/beaglebone-black
--- a/beaglebone-black/ch02.rst
+++ b/beaglebone-black/ch02.rst
-.. _bbb-Change-History:
+.. _beagleboneblack-Change-History:

 Change History
 ##################

 This section describes the change history of this document and board.
 Document changes are not always a result of a board change. A board
-change will always result in a document change.
+change will always connectivityresult in a document change.

 Document Change History
 ---------------------------

-.. list-table:: Change History
+.. list-table:: AsciiDoc Change History
   :header-rows: 1
   :class: longtable
   :widths: 8, 60, 25,7
+   :align: center

   * - Rev
     - Changes
@@ -109,10 +110,59 @@ Document Change History
     - Numerous community edits and format changes to asciidoc.
     - May 6, 2020
     - JK
-   
+   * - C.3
+     - Added information for board rev C3.
+     - August 24, 2021
+     - JK
+
 Board Changes
 -----------------

+Rev C3
+********
+
+PCB revision C.
+
+* Updated microSD card cage due to availability. See https://github.com/beagleboard/beaglebone-black/issues/6. Added series resistors and depopulated C5.
+* Added reset option (GPIO1_8) for Ethernet PHY to avoid possible start-up issue. See https://github.com/beagleboard/beaglebone-black/issues/4.
+* Added series resistors to MMC1 lines and depopulated C24.
+* Connected pin A6 of J5 on U13 (eMMC IC) to DGND.
+* Changed USB1_VBUS series resistor to 0 ohm.
+* Change required PCB revision to C.
+
+Initial boxes mistakenly say rev C1.
+
+Rev C2
+*******
+
+PCB revision B6.
+
+* Update memories based on availability. See https://github.com/beagleboard/beaglebone-black/commit/74914bd01efeb61376ec3dda4bf9143ad2bb635c.
+   
+  * DDR3:
+    
+    * Kingston D2516EC4BXGGB-U
+  
+  * eMMC:
+    
+    * Kingston MMC04G-M627-X02U
+
+Rev C1
+********
+
+PCB revision B6.
+
+* Update memories based on availability. See https://github.com/beagleboard/beaglebone-black/commit/5787736d816832cc8cc9629d19f334b6a12e67f9.
+  
+  * DDR3:
+    
+    * Micron MT41K256M16TW-107:P
+  
+  * eMMC:
+    
+    * Micron MTFC4GACAJCN-1M WT
+    * Kingston EMMC04G-S100-A08U
+
 Rev C
 ***********


--- a/beaglebone-black/ch03.rst
+++ b/beaglebone-black/ch03.rst
+.. _beagleboneblack-connectivity:

 Connecting Up Your BeagleBone Black
 #######################################
@@ -72,7 +73,8 @@ Firefox or Chrome on the PC, IEx will not work properly. <<figure-2>>
 shows this configuration.

 .. figure:: media/image8.jpg
-   :width: 400px
+   :width: 632px
+   :height: 166px
   :align: center
   :alt: Tethered Configuration

@@ -92,17 +94,19 @@ Connect the Cable to the Board
 1. Connect the small connector on the USB cable to the board as shown in *figure-3*. The connector is on the bottom side of the board.

 .. figure:: media/image9.jpg
-   :width: 400px
+   :width: 451px
+   :height: 206px
   :align: center
   :alt: USB Connection to the Board

   USB Connection to the Board

 2.  Connect the large connector of the USB cable to your PC or laptop USB port.
-3.  The board will power on and the power LED will be on as shown in *figure-4* below.
+3.  The board will power on and the power LED will be on as shown in figure below.

 .. figure:: media/image10.jpg
-   :width: 400px
+   :width: 401px
+   :height: 267px
   :align: center
   :alt: Board Power LED

@@ -112,6 +116,7 @@ Connect the Cable to the Board

 .. figure:: media/image11.jpg
   :width: 400px
+   :height: 254px
   :align: center
   :alt: Board Boot Status

@@ -140,7 +145,8 @@ however require certain common PC accessories. These accessories and
 instructions are described in the following section.

 .. figure:: media/image12.jpg
-   :width: 400px
+   :width: 356px
+   :height: 409px
   :align: center
   :alt: Desktop Configuration

@@ -168,7 +174,8 @@ Connecting Up the Board
 1. Connect the big end of the HDMI cable as shown in *figure-7* to your HDMI monitor. Refer to your monitor Owner’s Manual for the location of your HDMI port. If you have a DVI-D Monitor go to *Step 3*, otherwise proceed to *Step 4* .

 .. figure:: media/image13.jpg
-   :width: 400px
+   :width: 260px
+   :height: 95px
   :align: center
   :alt: Connect microHDMI Cable to the Monitor

@@ -177,7 +184,8 @@ Connecting Up the Board
 2.  If you have a DVI-D monitor you must use a DVI-D to HDMI adapter in addition to your HDMI cable. An example is shown in *figure-8* below from two perspectives. If you use this configuration, you will not have audio support.

 .. figure:: media/image14.jpg
-   :width: 400px
+   :width: 243px
+   :height: 243px
   :align: center
   :alt: DVI-D to HDMI Adapter

@@ -186,7 +194,8 @@ Connecting Up the Board
 3.  If you have a single wireless keyboard and mouse combination such as seen in *figure-9* below, you need to plug the receiver in the USB host port of the board as shown in *figure-10* .

 .. figure:: media/image16.jpg
-   :width: 400px
+   :width: 237px
+   :height: 108px
   :align: center
   :alt: Wireless Keyboard and Mouse Combo

@@ -194,16 +203,18 @@ Connecting Up the Board


 .. figure:: media/image17.jpg
-   :width: 400px
+   :width: 279px
+   :height: 222px
   :align: center
   :alt: Connect Keyboard and Mouse Receiver to the Board

   Connect Keyboard and Mouse Receiver to the Board

-If you have a wired USB keyboard requiring two USB ports, you will need a HUB similar to the ones shown in *figure-11* . You may want to have more than one port for other devices. Note that the board can only supply up to 500mA, so if you plan to load it down, it will need to be externally powered.
+If you have a wired USB keyboard requiring two USB ports, you will need a HUB similar to the ones shown in figure below . You may want to have more than one port for other devices. Note that the board can only supply up to 500mA, so if you plan to load it down, it will need to be externally powered.

 .. figure:: media/image18.jpg
-   :width: 400px
+   :width: 509px
+   :height: 152px
   :align: center
   :alt: Keyboard and Mouse Hubs

@@ -211,19 +222,21 @@ If you have a wired USB keyboard requiring two USB ports, you will need a HUB si

 4. Connect the Ethernet Cable

-If you decide you want to connect to your local area network, an Ethernet cable can be used. Connect the Ethernet Cable to the Ethernet port as shown in *figure-12* . Any standard 100M Ethernet cable should work.
+If you decide you want to connect to your local area network, an Ethernet cable can be used. Connect the Ethernet Cable to the Ethernet port as shown in figure below . Any standard 100M Ethernet cable should work.

 .. figure:: media/image24.jpg
-   :width: 400px
+   :width: 433px
+   :height: 264px
   :align: center
   :alt: Ethernet Cable Connection

   Ethernet Cable Connection

-5. The final step is to plug in the DC power supply to the DC power jack as shown in *figure-13* below.
+5. The final step is to plug in the DC power supply to the DC power jack as shown in figure below.

 .. figure:: media/image25.jpg
-   :width: 400px
+   :width: 618px
+   :height: 298px
   :align: center
   :alt: External DC Power

@@ -232,7 +245,8 @@ If you decide you want to connect to your local area network, an Ethernet cable
 6. The cable needed to connect to your display is a microHDMI to HDMI. Connect the microHDMI connector end to the board at this time. The connector is on the bottom side of the board as shown in *figure-14* below.

 .. figure:: media/image26.jpg
-   :width: 400px
+   :width: 540px
+   :height: 227
   :align: center
   :alt: Connect microHDMI Cable to the Board 

@@ -245,7 +259,8 @@ The connector is fairly robust, but we suggest that you not use the cable as a l
 As soon as the power is applied to the board, it will start the booting up process. When the board starts to boot the LEDs will come on in sequence as shown in *figure-15* below. It will take a few seconds for the status LEDs to come on, so be patient. The LEDs will be flashing in an erratic manner as it boots the Linux kernel.

 .. figure:: media/image11.jpg
-   :width: 400px
+   :width: 541px
+   :height: 254px
   :align: center
   :alt: Board Boot Status

@@ -270,7 +285,8 @@ once the Linux kernel has booted.
   d. And at this point you are ready to go! *figure-16* shows the desktop after booting.

 .. figure:: media/image27.jpg
-   :width: 400px
+   :width: 513px
+   :height: 288px
   :align: center
   :alt: Desktop Screen


--- a/beaglebone-black/ch04.rst
+++ b/beaglebone-black/ch04.rst
+.. _beagleboneblack-overview:
+
 BeagleBone Black Overview
 #############################

@@ -102,21 +104,26 @@ the reasons for the differences.

 * GPIO3_21 has a 24.576 MHZ clock on it.
  
-  * This is required by the HDMI Framer for Audio purposes. We needed to run a clock into the processor to generate the correct clock frequency.
-  
-The pin on the processor was already routed to the expansion header. In order not to remove this feature on the expansion header, it was left
-connected. In order to use the pin as a GPIO pin, you need to disable the clock. While this disables audio to the HDMI, the fact that you want to use this pin for something else, does the same thing.
+  * This is required by the HDMI Framer for Audio purposes. 
+    We needed to run a clock into the processor to generate the correct clock frequency. 
+    The pin on the processor was already routed to the expansion header. In order not 
+    to remove this feature on the expansion header, it was left connected. In order to 
+    use the pin as a GPIO pin, you need to disable the clock. While this disables audio 
+    to the HDMI, the fact that you want to use this pin for something else, does the 
+    same thing.

 BeagleBone Black Features and Specification
 -----------------------------------------------

 This section covers the specifications and features of the board and
 provides a high level description of the major components and interfaces
-that make up the board.
+that make up the board. table below provides a list of the features.


 .. list-table:: BeagleBone Black Features
   :header-rows: 1
+   :widths: 20 80
+   :class: longtable

   * -
     - Feature
@@ -181,8 +188,12 @@ the various components on the board.
 Connectors, LEDs, and Switches
 ************************************

+figure below shows the locations of the connectors, LEDs, and
+switches on the PCB layout of the board.
+
 .. figure:: media/image28.jpg
-   :width: 400px
+   :width: 509px
+   :height: 340px
   :align: center
   :alt: Connectors, LEDs and Switches

@@ -203,8 +214,12 @@ Connectors, LEDs, and Switches
 Key Components
 ********************

+figure below shows the locations of the key components on the PCB
+layout of the board.
+
 .. figure:: media/image29.jpg
-   :width: 400px
+   :width: 575px
+   :height: 417px
   :align: center
   :alt: Key Components


--- a/beaglebone-black/ch05.rst
+++ b/beaglebone-black/ch05.rst
+.. _beagleboneblack-specifications:
+
 BeagleBone Black High Level Specification
 #############################################

@@ -8,7 +10,8 @@ Block Diagram
 -----------------

 .. figure:: media/image30.jpg
-   :width: 400px
+   :width: 512px
+   :height: 454px
   :align: center
   :alt: BeagleBone Black Key Components

@@ -266,4 +269,4 @@ not be present or are limited to the BeagleBone Black. These include:
 * Another option is to use the microSD or serial boot modes and not use the eMMC.
 * The power expansion header is not on the BeagleBone Black so those functions are not supported.

-For more information on cape support refer to *section-9*.
+For more information on cape support refer to :ref:`beagleboneblack-mechanical` section.
--- a/beaglebone-black/ch06.rst
+++ b/beaglebone-black/ch06.rst
+.. _beagleboneblack-hardware:
+
 Detailed Hardware Design
 ############################

@@ -6,7 +8,8 @@ This can be useful for interfacing, writing drivers, or using it to help
 modify specifics of your own design.

 .. figure:: media/image30.jpg
-   :width: 400px
+   :width: 521px
+   :height: 454px
   :align: center
   :alt: BeagleBone Black Block Diagram

@@ -16,7 +19,8 @@ Power Section
 -----------------

 .. figure:: media/image31.png
-   :width: 400px
+   :width: 417px
+   :height: 278px
   :align: center
   :alt: High Level Power Block Diagram

@@ -64,7 +68,8 @@ For more information on the *TPS65217C*, refer to
 `http://www.ti.com/product/tps65217C <http://www.ti.com/product/tps65217C>`_

 .. figure:: media/image37.png
-   :width: 400px
+   :width: 550px
+   :height: 629px
   :align: center
   :alt: TPS65217C Block Diagram

@@ -74,7 +79,8 @@ DC Input
 **************

 .. figure:: media/image38.png
-   :width: 400px
+   :width: 458px
+   :height: 408px
   :align: center
   :alt: TPS65217 DC Connection

@@ -105,7 +111,8 @@ of the expansion header for use by a cape. *Figure 24* is the connection
 of the USB power input on the PMIC.

 .. figure:: media/image96.png
-   :width: 400px
+   :width: 519px
+   :height: 622px
   :align: center
   :alt: USB Power Connections

@@ -163,6 +170,9 @@ via a cape if desired. The four signals are listed below in *table-3* .

 .. list-table:: BeagleBone Black Battery Pins
   :header-rows: 1
+   :class: longtable
+   :widths: 15 15 70
+   :align: center

   * - PIN
     - DESIGNATION
@@ -207,6 +217,9 @@ following configuration:

 .. list-table:: BeagleBone Black Power Consumption(mA@5V)
   :header-rows: 1
+   :class: longtable
+   :widths: 40 20 20 20
+   :align: center

   * - MODE
     - USB
@@ -294,7 +307,8 @@ Power Rails
 *****************

 .. figure:: media/image39.jpg
-   :width: 400px
+   :width: 562px
+   :height: 505px
   :align: center
   :alt: Power Rails

@@ -357,7 +371,8 @@ diagrams. It is from the processor datasheet supplied by Texas
 Instruments.

 .. figure:: media/image40.png
-   :width: 400px
+   :width: 547px
+   :height: 397px
   :align: center
   :alt: Power Rail Power Up Sequencing

@@ -369,7 +384,8 @@ powers up and the voltages on each rail. The power sequencing starts at
 You can refer to the TPS65217C datasheet for more information.

 .. figure:: media/image41.png
-   :width: 400px
+   :width: 225px
+   :height: 188px
   :align: center
   :alt: TPS65217C Power Sequencing Timing

@@ -387,12 +403,13 @@ issue that caused it to shut down. The connection of the LED is shown in
 TPS65217C Power Up Process
 *********************************

-*figure-28* shows the interface between the **TPS65217C** and the
+Figure below shows the interface between the **TPS65217C** and the
 processor. It is a cut from the PDF form of the schematic and reflects
 what is on the schematic.

 .. figure:: media/image42.jpg
   :width: 400px
+   :height: 185px
   :align: center
   :alt: Power Processor Interfaces

@@ -486,11 +503,12 @@ processor.
 Description
 *****************

-*figure-29* is a high level block diagram of the processor. For more information on the processor, go to
+Figure below shows is a high level block diagram of the processor. For more information on the processor, go to
 `http://www.ti.com/product/am3358 <http://www.ti.com/product/am3358>`_

 .. figure:: media/image43.png
-   :width: 400px
+   :width: 503px
+   :height: 511px
   :align: center
   :alt: Sitara AM3358BZCZ Block Diagram

@@ -503,6 +521,9 @@ High Level Features

 .. list-table:: Processor Features
   :header-rows: 1
+   :class: longtable
+   :align: center
+   :widths: 25 30 25 20

   * - Operating Systems
     - Linux, Android, Windows Embedded CE,QNX,ThreadX 
@@ -576,7 +597,8 @@ Crystal Circuitry
 ***********************

 .. figure:: media/image44.png
-   :width: 400px
+   :width: 570px
+   :height: 223px
   :align: center
   :alt: Processor Crystals

@@ -603,7 +625,8 @@ using an open drain buffer. These ensure that the line does not
 momentarily go high on power up.

 .. figure:: media/image45.png
-   :width: 400px
+   :width: 568px
+   :height: 333px
   :align: center
   :alt: Board Reset Circuitry

@@ -669,7 +692,8 @@ are disabled during powerdown. Input buffers (excluding CKE and RESET#)
 are disabled during SELF REFRESH. CKE is referenced to VREFCA.

 .. figure:: media/image46.png
-   :width: 400px
+   :width: 566px
+   :height: 525px
   :align: center
   :alt: DDR3L Memory Design

@@ -710,7 +734,8 @@ rail that powers the processor DDR rail and the DDR3L device itself.
 connection to the DDR3L memory device and the processor.

 .. figure:: media/image47.jpg
-   :width: 400px
+   :width: 376px
+   :height: 269px
   :align: center
   :alt: DDR3L VREF Design

@@ -766,7 +791,8 @@ Pullup resistors are used to increase the rise time on the signals to
 compensate for any capacitance on the board.

 .. figure:: media/image48.png
-   :width: 400px
+   :width: 542px
+   :height: 224px
   :align: center
   :alt: eMMC Memory Design

@@ -775,7 +801,8 @@ compensate for any capacitance on the board.
 The pins used by the eMMC1 in the boot mode are listed below in *Table 6*.

 .. figure:: media/image49.png
-   :width: 400px
+   :width: 528px
+   :height: 112px
   :align: center
   :alt: eMMC Boot Pins

@@ -811,6 +838,9 @@ the contents of the EEPROM.

 .. list-table:: EEPROM Contents
   :header-rows: 1
+   :class: longtable
+   :align: center
+   :widths: 20 15 65

   * - Name 
     - Size (bytes) 
@@ -844,7 +874,8 @@ the contents of the EEPROM.
     - Available space for other non-volatile codes/data

 .. figure:: media/image50.png
-   :width: 400px
+   :width: 473px
+   :height: 194px
   :align: center
   :alt: EEPROM Design Rev A5

@@ -869,7 +900,8 @@ microSD Design
 ********************

 .. figure:: media/image51.png
-   :width: 400px
+   :width: 550px
+   :height: 216px
   :align: center
   :alt: microSD Design

@@ -905,7 +937,8 @@ GPIO pins on the processor. *Figure 37* shows the interfaces for the
 user LEDs.

 .. figure:: media/image52.png
-   :width: 400px
+   :width: 570px
+   :height: 290px
   :align: center
   :alt: User LEDs

@@ -916,7 +949,8 @@ boards.

 .. list-table:: User LED Control Signals/Pins
   :header-rows: 1
-
+   :class: longtable
+   :align: center

   * - LED 
     - GPIO SIGNAL 
@@ -966,7 +1000,8 @@ to determine the boot order. S2 is used to change the level of one bit
 from HI to LO which changes the boot order.

 .. figure:: media/image53.png
-   :width: 400px
+   :width: 448px
+   :height: 367px
   :align: center
   :alt: Processor Boot Configuration Design

@@ -986,7 +1021,8 @@ Based on the selected option found in *figure-39* below, each of the
 boot sequences for each of the two settings is shown.

 .. figure:: media/image54.jpg
-   :width: 400px
+   :width: 601px
+   :height: 130px
   :align: center
   :alt: Processor Boot Configuration

@@ -1015,7 +1051,8 @@ described in the following sections.
 **********************************

 .. figure:: media/image55.png
-   :width: 400px
+   :width: 448px
+   :height: 312px
   :align: center
   :alt: Ethernet Processor Interface

@@ -1031,7 +1068,8 @@ The off board side of the PHY connections are shown in *Figure 41*
 below.

 .. figure:: media/image56.png
-   :width: 400px
+   :width: 570px
+   :height: 347px
   :align: center
   :alt: Ethernet Connector Interface

@@ -1043,7 +1081,8 @@ Ethernet PHY Power, Reset, and Clocks
 *******************************************

 .. figure:: media/image57.png
-   :width: 400px
+   :width: 570px
+   :height: 367px
   :align: center
   :alt: Ethernet PHY, Power, Reset, and Clocks

@@ -1093,7 +1132,8 @@ value pull up resistors are used. *Figure 43* below shows the three mode
 pin resistors.

 .. figure:: media/image97.png
-   :width: 400px
+   :width: 386px
+   :height: 349px
   :align: center
   :alt: Ethernet PHY Mode Pins

@@ -1124,6 +1164,8 @@ the highest compatible resolution is selected.

 .. list-table:: HDMI Supported Monitor Resolutions
   :header-rows: 1
+   :class: longtable
+   :align: center

   * - RESOLUTION 
     - AUDIO
@@ -1198,7 +1240,8 @@ addition to the data signals are the VSYNC, HSYNC, DE, and PCLK signals
 that round out the video interface from the processor.

 .. figure:: media/image58.png
-   :width: 400px
+   :width: 449px
+   :height: 481px
   :align: center
   :alt: HDMI Framer Processor Interface

@@ -1215,7 +1258,8 @@ tied low. The I2C interface supports both 400kHz and 100KhZ operation.
 *Table 10* shows the I2C address.

 .. figure:: media/image59.png
-   :width: 400px
+   :width: 527px
+   :height: 72px
   :align: center
   :alt: TDA19988 I2C Address

@@ -1256,7 +1300,8 @@ if the need was there to use the pin on the expansion header. *Figure
 45* shows the oscillator circuitry.

 .. figure:: media/image60.png
-   :width: 400px
+   :width: 575px
+   :height: 169px
   :align: center
   :alt: 24.576MHZ Oscillator

@@ -1270,7 +1315,8 @@ voltage rails for the device are at 1.8V. A filter is provided to
 minimize any noise from the 1.8V rail getting back into the device.

 .. figure:: media/image64.png
-   :width: 400px
+   :width: 550px
+   :height: 315px
   :align: center
   :alt: HDMI Power Connections

@@ -1286,7 +1332,8 @@ HDMI Connector Interface
 and the connector.

 .. figure:: media/image65.png
-   :width: 400px
+   :width: 521px
+   :height: 430px
   :align: center
   :alt: Connector Interface Circuitry

@@ -1304,7 +1351,8 @@ single USB Type A female connector. <<figure-48>> is the design of the USB
 Host circuitry.

 .. figure:: media/image66.png
-   :width: 400px
+   :width: 570px
+   :height: 205px
   :align: center
   :alt: USB Host circuit

@@ -1370,7 +1418,8 @@ PRU-ICSS Block Diagram
 *****************************

 .. figure:: media/image67.png
-   :width: 400px
+   :width: 427px
+   :height: 275px
   :align: center
   :alt: PRU-ICSS Block Diagram

@@ -1387,235 +1436,213 @@ for example. Listed below is what ports can be accessed on each PRU.
 * 13 outputs or 14 inputs
 * UART0_TXD, UART0_RXD, UART0_CTS, UART0_RTS

-.. list-table:: PRU0 and PRU1 Access
+.. list-table:: P8 PRU0 and PRU1 Access
   :header-rows: 1
+   :class: longtable
+   :align: center
+   :widths: 5 8 15 24 24 24

-   * - 
-     - PIN 
+   * - PIN 
     - PROC 
     - NAME 
     - 
     -
     -
-   * - P8 
-     - 11 
+   * - 11 
     - R12 
     - GPIO1_13 
     - 
     - pr1_pru0_pru_r30_15 (Output)  
     - 
-   * - 
-     - 12 
+   * - 12 
     - T12 
     - GPIO1_12 
     - 
     - pr1_pru0_pru_r30_14 (Output) 
     - 
-   * - 
-     - 15 
+   * - 15 
     - U13 
     - GPIO1_15 
     - 
     - pr1_pru0_pru_r31_15 (Input) 
     - 
-   * - 
-     - 16 
+   * - 16 
     - V13 
     - GPIO1_14 
     - 
     - pr1_pru0_pru_r31_14 (Input) 
     - 
-   * - 
-     - 20 
+   * - 20 
     - V9 
     - GPIO1_31 
     - pr1_pru1_pru_r30_13 (Output) 
     - pr1_pru1_pru_r31_13 (INPUT) 
     - 
-   * -
-     - 21 
+   * - 21 
     - U9 
     - GPIO1_30 
     - pr1_pru1_pru_r30_12 (Output) 
     - pr1_pru1_pru_r31_12 (INPUT) 
     - 
-   * - 
-     - 27 
+   * - 27 
     - U5 
     - GPIO2_22 
     - pr1_pru1_pru_r30_8 (Output) 
     - pr1_pru1_pru_r31_8 (INPUT) 
     - 
-   * - 
-     - 28 
+   * - 28 
     - V5 
     - GPIO2_24 
     - pr1_pru1_pru_r30_10 (Output) 
     - pr1_pru1_pru_r31_10 (INPUT) 
     - 
-   * -
-     - 29 
+   * - 29 
     - R5 
     - GPIO2_23 
     - pr1_pru1_pru_r30_9 (Output) 
     - pr1_pru1_pru_r31_9 (INPUT) 
     - 
-   * - 
-     - 39 
+   * - 39 
     - T3 
     - GPIO2_12 
     - pr1_pru1_pru_r30_6 (Output) 
     - pr1_pru1_pru_r31_6 (INPUT) 
     - 
-   * -
-     - 40 
+   * - 40 
     - T4 
     - GPIO2_13 
     - pr1_pru1_pru_r30_7 (Output) 
     - pr1_pru1_pru_r31_7 (INPUT) 
     -
-   * - 
-     - 41 
+   * - 41 
     - T1 
     - GPIO2_10 
     - pr1_pru1_pru_r30_4 (Output) 
     - pr1_pru1_pru_r31_4 (INPUT) 
     - 
-   * -
-     - 42 
+   * - 42 
     - T2 
     - GPIO2_11 
     - pr1_pru1_pru_r30_5 (Output) 
     - pr1_pru1_pru_r31_5 (INPUT) 
     - 
-   * - 
-     - 43 
+   * - 43 
     - R3 
     - GPIO2_8 
     - pr1_pru1_pru_r30_2 (Output) 
     - pr1_pru1_pru_r31_2 (INPUT) 
     - 
-   * -
-     - 44 
+   * - 44 
     - R4 
     - GPIO2_9 
     - pr1_pru1_pru_r30_3 (Output) 
     - pr1_pru1_pru_r31_3 (INPUT) 
     - 
-   * -
-     - 45 
+   * - 45 
     - R1 
     - GPIO2_6 
     - pr1_pru1_pru_r30_0 (Output) 
     - pr1_pru1_pru_r31_0 (INPUT) 
     - 
-   * -
-     - 46 
+   * - 46 
     - R2 
     - GPIO2_7 
     - pr1_pru1_pru_r30_1 (Output) 
     - pr1_pru1_pru_r31_1 (INPUT) 
     - 
-   * -
-     -
-     -
-     -
-     -
+
+
+.. list-table:: P9 PRU0 and PRU1 Access
+   :header-rows: 1
+   :class: longtable
+   :align: center
+   :widths: 5 8 15 24 24 24
+
+   * - PIN 
+     - PROC 
+     - NAME 
+     - 
     -
     -
-   * - P9 
-     - 17 
+   * - 17 
     - A16 
     - I2C1_SCL 
     - pr1_uart0_txd 
     - 
     -
-   * -
-     - 18 
+   * - 18 
     - B16 
     - I2C1_SDA 
     - pr1_uart0_rxd 
     - 
     -
-   * -
-     - 19 
+   * - 19 
     - D17 
     - I2C2_SCL 
     - pr1_uart0_rts_n 
     - 
     -
-   * -
-     - 20 
+   * - 20 
     - D18 
     - I2C2_SDA 
     - pr1_uart0_cts_n 
     - 
     - 
-   * -
-     - 21 
+   * - 21 
     - B17 
     - UART2_TXD 
     - pr1_uart0_rts_n 
     - 
     -
-   * -
-     - 22 
+   * - 22 
     - A17 
     - UART2_RXD 
     - pr1_uart0_cts_n 
     - 
     -
-   * -
-     - 24 
+   * - 24 
     - D15 
     - UART1_TXD 
     - pr1_uart0_txd 
     - pr1_pru0_pru_r31_16 (Input) 
     - 
-   * -
-     - 25 
+   * - 25 
     - A14 
     - GPIO3_21
     - pr1_pru0_pru_r30_5 (Output) 
     - pr1_pru0_pru_r31_5 (Input) 
     - 
-   * -
-     - 26 
+   * - 26 
     - D16 
     - UART1_RXD 
     - pr1_uart0_rxd 
     - pr1_pru1_pru_r31_16 
     -
-   * -
-     - 27 
+   * - 27 
     - C13 
     - GPIO3_19 
     - pr1_pru0_pru_r30_7 (Output) 
     - pr1_pru0_pru_r31_7 (Input) 
     - 
-   * - 
-     - 28 
+   * - 28 
     - C12 
     - SPI1_CS0 
     - eCAP2_in_PWM2_out 
     - pr1_pru0_pru_r30_3 (Output) 
     - pr1_pru0_pru_r31_3 (Input)
-   * -
-     - 29 
+   * - 29 
     - B13 
     - SPI1_D0 
     - pr1_pru0_pru_r30_1 (Output) 
     - pr1_pru0_pru_r31_1 (Input) 
     - 
-   * -
-     - 30 
+   * - 30 
     - D12 
     - SPI1_D1 
     - pr1_pru0_pru_r30_2 (Output) 
     - pr1_pru0_pru_r31_2 (Input) 
     -
-   * -
-     - 31 
+   * - 31 
     - A13 
     - SPI1_SCLK 
     - pr1_pru0_pru_r30_0 (Output) 

--- a/beaglebone-black/ch07.rst
+++ b/beaglebone-black/ch07.rst
+.. _beagleboneblack-connectors:
+
 Connectors
 ##############

@@ -54,6 +56,11 @@ THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.*

 *NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES HIGH.*

+.. raw:: latex
+
+  \begin{landscape}
+  \tiny
+
 .. list-table:: Expansion Header P8 Pinout
   :header-rows: 1

@@ -564,6 +571,10 @@ THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.*
     - pr1_pru1_pru_r31_1
     - gpio2[7]

+.. raw:: latex
+
+  \end{landscape}
+

 Connector P9
 ******************
@@ -601,6 +612,10 @@ THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.*
 
 * Both of these signals connect to pin 42 of P11. Resistors are installed that allow for the GPIO3_18 connection to be removed by removing R202. The intent is to allow the SW to use either of these signals, on pin 42. SW should set the unused pin in input mode when using the other pin. This allowed us to get an extra signal out to the expansion header.

+.. raw:: latex
+
+  \begin{landscape}
+  \tiny

 .. list-table:: Expansion Header P9 Pinout
   :header-rows: 1
@@ -1067,8 +1082,12 @@ THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.*
     -
     - 
     -
-    
-7.2 Power Jack
+
+.. raw:: latex
+
+  \end{landscape}
+
+Power Jack
 --------------

 The DC power jack is located next to the RJ45 Ethernet connector as
@@ -1078,7 +1097,8 @@ the original BeagleBone. The connector has a 2.1mm diameter center post


 .. figure:: media/image69.jpg
-   :width: 400px
+   :width: 579px
+   :height: 411px
   :align: center
   :alt: 5VDC Power Jack

@@ -1088,7 +1108,7 @@ The board requires a regulated 5VDC +/-.25V supply at 1A. A higher
 current rating may be needed if capes are plugged into the expansion
 headers. Using a higher current power supply will not damage the board.

-7.3 USB Client
+USB Client
 --------------

 The USB Client connector is accessible on the bottom side of the board
@@ -1099,7 +1119,8 @@ board.


 .. figure:: media/image71.jpg
-   :width: 400px
+   :width: 633px
+   :height: 454px
   :align: center
   :alt: USB Client

@@ -1108,7 +1129,7 @@ board.
 This port is a USB Client only interface and is intended for connection
 to a PC.

-7.4 USB Host
+USB Host
 ------------

 There is a single USB Host connector on the board and is shown in
@@ -1116,7 +1137,8 @@ There is a single USB Host connector on the board and is shown in


 .. figure:: media/image71.jpg
-   :width: 400px
+   :width: 593px
+   :height: 387px
   :align: center
   :alt: USB Host Connector

@@ -1130,8 +1152,9 @@ Serial Header
 Each board has a debug serial interface that can be accessed by using a special serial cable that is plugged into the serial header as shown in *Figure 54* below.


-.. figure:: media/image73.jpg
-   :width: 400px
+.. figure:: media/image71.jpg
+   :width: 527px
+   :height: 351px
   :align: center
   :alt: Serial Debug Header

@@ -1142,8 +1165,9 @@ these signals are 3.3V. In order to access these signals, a FTDI USB to
 Serial cable is recommended as shown in *Figure 55* below.


-.. figure:: media/image71.jpg
-   :width: 400px
+.. figure:: media/image73.jpg
+   :width: 428px
+   :height: 162px
   :align: center
   :alt: PRU-ICSS Block Diagram

@@ -1163,6 +1187,8 @@ Table is the pinout of the connector as reflected in the schematic. It is the sa

 .. list-table:: J1 Serial Header Pins
   :header-rows: 1
+   :class: longtable
+   :align: center
   :widths: auto

   * - PIN NUMBER 
@@ -1176,13 +1202,14 @@ Table is the pinout of the connector as reflected in the schematic. It is the sa


 .. figure:: media/image75.jpg
-   :width: 400px
+   :width: 373px
+   :height: 387px
   :align: center
   :alt: Serial Header

   Serial Header

-7.6 HDMI
+HDMI
 --------

 Access to the HDMI interface is through the HDMI connector that is
@@ -1190,7 +1217,8 @@ located on the bottom side of the board as shown in *Figure 57* below.


 .. figure:: media/image71.jpg
-   :width: 400px
+   :width: 579px
+   :height: 387px
   :align: center
   :alt: HDMI Connector

@@ -1203,13 +1231,15 @@ be purchased from several different sources.


 .. figure:: media/image77.jpg
-   :width: 400px
+   :width: 196px
+   :height: 196px
+   :class: longtable
   :align: center
   :alt: HDMI Cable

   HDMI Cable

-7.7 microSD
+microSD
 -----------

 A microSD connector is located on the back or bottom side of the board
@@ -1218,7 +1248,8 @@ board.


 .. figure:: media/image71.jpg
-   :width: 400px
+   :width: 579px
+   :height: 438px
   :align: center
   :alt: microSD Connector

@@ -1233,15 +1264,16 @@ the connector.

 Do not pull the SD card out or you could damage the connector.

-7.8 Ethernet
+Ethernet
 ------------

 The board comes with a single 10/100 Ethernet interface located next to
-the power jack as shown in *Figure 60*.
+the power jack as shown in Figure below.


 .. figure:: media/image71.jpg
-   :width: 400px
+   :width: 579px
+   :height: 387px
   :align: center
   :alt: Ethernet Connector


--- a/beaglebone-black/ch08.rst
+++ b/beaglebone-black/ch08.rst
+.. _beagleboneblack-capes:
+
 Cape Board Support
 ######################

@@ -57,6 +59,8 @@ These signals are listed in *Table 15* below.

 .. list-table:: P8 LCD Conflict Pins
   :header-rows: 1
+   :class: longtable
+   :align: center

   * - PIN 
     - PROC 
@@ -169,7 +173,8 @@ The proper mode is MODE2.

 .. list-table:: P8 eMMC Conflict Pins
   :header-rows: 1
-
+   :align: center
+   :class: longtable

   * - PIN 
     - PROC 
@@ -247,7 +252,7 @@ this. No, we will not designate a pin for this function. It will be
 determined on a cape by cape basis by the designer of the respective
 cape.

-8.2 EEPROM
+EEPROM
 ----------

 Each cape must have its own EEPROM containing information that will
@@ -270,7 +275,8 @@ a 64-byte page write buffer and supports the Standard (100 kHz), Fast


 .. figure:: media/image78.png
-   :width: 400px
+   :width: 509px
+   :height: 228px
   :align: center
   :alt: Expansion Board EEPROM Without Write Protect

@@ -344,10 +350,9 @@ discretion of the cape designer.
 *Variable & MAC Memory*
 VDD_3V3B

-
-
 .. figure:: media/image79.png
-   :width: 400px
+   :width: 567px
+   :height: 189px
   :align: center
   :alt: Expansion Board EEPROM Write Protect

@@ -364,6 +369,8 @@ by the user when the EEPROM contents are dumped.

 .. list-table:: Expansion Board EEPROM
   :header-rows: 1
+   :class: longtable
+   :align: center

   * - Name
     - Offset
@@ -461,6 +468,8 @@ for the AIN signals.

 .. list-table:: EEPROM Pin Usage
   :header-rows: 1
+   :class: longtable
+   :align: center


   * - `+` 
@@ -1619,11 +1628,12 @@ as they appear on the BeagleBone Black.:


 .. figure:: media/image80.png
-   :width: 400px
+   :width: 530px
+   :height: 468px
   :align: center
-   :alt: 63*
+   :alt: Boot signals

-   63*
+   Boot signals

 If you plan to use any of these signals, then on power up, these pins
 should not be driven. If you do, it can affect the boot mode of the
@@ -1659,7 +1669,7 @@ configurations for the expansion headers:
 The following sections describe how the connectors are to be implemented
 and used for each of the different configurations.

-Non-StaCape
+Non-Stacking Headers-Single Cape
 **************************************

 For non-stacking capes single configurations or where the cape can be
@@ -1670,7 +1680,8 @@ dual row 23 position 2.54mm x 2.54mm connectors.


 .. figure:: media/image81.jpg
-   :width: 400px
+   :width: 65px
+   :height: 90px
   :align: center
   :alt: Single Expansion Connector

@@ -1684,7 +1695,8 @@ of the dual row headers.


 .. figure:: media/image82.jpg
-   :width: 400px
+   :width: 575px
+   :height: 54px
   :align: center
   :alt: Single Cape Expansion Connector

@@ -1709,7 +1721,8 @@ the BeagleBone Black

 .. list-table:: Single Cape Connectors
   :header-rows: 1
-
+   :class: longtable
+   :align: center

   * - SUPPLIER 
     - PARTNUMBER
@@ -1734,7 +1747,8 @@ as well as long as the contact area is gold. Other possible sources are
 Sullins and Samtec for these connectors. You will need to ensure the
 depth into the connector is sufficient

-Main Ex*************************************
+Main Expansion Headers-Stacking
+*************************************

 For stacking configuration, the two 46 pin expansion headers use the
 same connectors. *Figure 66* is a picture of the connector. These are
@@ -1743,7 +1757,8 @@ dual row 23 position 2.54mm x 2.54mm connectors.


 .. figure:: media/image83.jpg
-   :width: 400px
+   :width: 69px
+   :height: 90px
   :align: center
   :alt: Expansion Connector

@@ -1757,7 +1772,8 @@ connector configuration for the connector.


 .. figure:: media/image84.jpg
-   :width: 400px
+   :width: 575px
+   :height: 65px
   :align: center
   :alt: Stacked Cape Expansion Connector

@@ -1780,6 +1796,8 @@ The third part listed in *Table 20* will have insertion force issues.

 .. list-table:: Stacked Cape Connectors
   :header-rows: 1
+   :class: longtable
+   :align: center

   * - SUPPLIER    
     - PARTNUMBER      
@@ -1820,7 +1838,8 @@ nonstacking style connectors.


 .. figure:: media/image85.jpg
-   :width: 400px
+   :width: 575px
+   :height: 71px
   :align: center
   :alt: Stacked w/Signal Stealing Expansion Connector

@@ -1851,7 +1870,8 @@ overhang.


 .. figure:: media/image86.jpg
-   :width: 400px
+   :width: 552px
+   :height: 314px
   :align: center
   :alt: Connector Pin Insertion Depth

@@ -1907,7 +1927,8 @@ are supplied by connector**P9**. The current ratings listed are per pin.

 .. list-table:: Expansion Voltages
   :header-rows: 1
-
+   :class: longtable
+   :align: center

   * - Current 
     - Name 
@@ -2000,7 +2021,8 @@ Standard Cape Size


 .. figure:: media/image87.jpg
-   :width: 400px
+   :width: 575px
+   :height: 369px
   :align: center
   :alt: Cape Board Dimensions


--- a/beaglebone-black/ch09.rst
+++ b/beaglebone-black/ch09.rst
+.. _beagleboneblack-mechanical:
+
 BeagleBone Black Mechanical
 ###############################

@@ -20,7 +22,8 @@ Silkscreen and Component Locations
 --------------------------------------

 .. figure:: media/image88.jpg
-   :width: 400px
+   :width: 530px
+   :height: 782px
   :align: center
   :alt: Board Dimensions

@@ -28,7 +31,8 @@ Silkscreen and Component Locations


 .. figure:: media/image89.jpg
-   :width: 400px
+   :width: 493px
+   :height: 818px
   :align: center
   :alt: Component Side Silkscreen

@@ -36,7 +40,8 @@ Silkscreen and Component Locations


 .. figure:: media/image90.jpg
-   :width: 400px
+   :width: 501px
+   :height: 772px
   :align: center
   :alt: Circuit Side Silkscreen


--- a/beaglebone-black/ch10.rst
+++ b/beaglebone-black/ch10.rst
+.. _beagleboneblack-pictures:
+
 Pictures
 #############


 .. figure:: media/image91.jpg
-   :width: 400px
+   :width: 476px
+   :height: 768px
   :align: center
   :alt: Top Side

   Top Side

 .. figure:: media/image92.jpg
-   :width: 400px
+   :width: 486px
+   :height: 764px
   :align: center
   :alt: Bottom Side


--- a/beaglebone-black/ch11.rst
+++ b/beaglebone-black/ch11.rst
+.. _beagleboneblack-support:
+
 Support Information
 ########################

@@ -45,21 +47,24 @@ filling out the form at `http://beagleboard.org/support/rma <http://beagleboard.


 .. figure:: media/image93.jpg
-   :width: 400px
+   :width: 518px
+   :height: 308px
   :align: center
   :alt: Initial Serial Number and Revision Locations
   
   Initial Serial Number and Revision Locations

 .. figure:: media/image94.jpg
-   :width: 400px
+   :width: 518px
+   :height: 230px
   :align: center
   :alt: Second Phase Serial Number and Revision Location

   Second Phase Serial Number and Revision Location

 .. figure:: media/image95.jpg
-   :width: 400px
+   :width: 575px
+   :height: 222px
   :align: center
   :alt: Third Phase Serial Number and Revision Location


--- a/beaglebone-black/index.rst
+++ b/beaglebone-black/index.rst
-.. _bbb-home:
+.. _beagleboneblack-home:

 BeagleBone Black
 ###################
@@ -6,6 +6,12 @@ BeagleBone Black
 BeagleBone Black is a low-cost, community-supported development platform for developers and hobbyists. 
 Boot Linux in under 10 seconds and get started on development in less than 5 minutes with just a single USB cable.

+.. image:: media/image1.jpg
+   :width: 598
+   :align: center
+   :height: 400
+   :alt: BeagleBone Black
+
 .. toctree::
   :maxdepth: 1

@@ -20,3 +26,4 @@ Boot Linux in under 10 seconds and get started on development in less than 5 min
   ch09.rst
   ch10.rst
   ch11.rst
+