Pratyush Yadav authored 4 years ago and Vignesh Raghavendra committed 4 years ago

Add nodes for Cadence CSI2RX, DPHY, and TI's CSI2RX wrapper. Also add
nodes for OV5640 which is the camera the drivers have been tested with.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

Faiz Abbas authored 4 years ago and Vignesh Raghavendra committed 4 years ago

Add two MCAN nodes present on the common processor board and set a
maximum data rate of 5 Mbps. Disable all other nodes for now.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>

Suman Anna authored 4 years ago and Vignesh Raghavendra committed 4 years ago

The commit 0f90c93f

 ("arm64: dts: ti: k3-j721e-common-proc-board:
add mcu cpsw nuss pinmux and phy defs") has added PPS support for
MCU CPSW CPTS by routing GenF1 output to MCU_CPTS_HW4_PUSH input using
timesync router. The timesync router is modeled as a pinctrl device with
the interrupt output configured as a pinmux setting. The TimeSync Interrupt
Router module registers are firewalled from SYSFW 2020.07-rc1 onwards,
and this pinmux setting results in a data abort and kernel boot failure.

Disable the PPS support and remove this pinmux setting to fix the kernel
boot. The required interrupt output setup needs to be done by System
Firmware through TI-SCI protocol.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

commit ae7fdac8

 upstream.

Sync MCU CPSW to LKML version as max as possible.
Used initial LKML commit to identify that code already upstream.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>

Update the INTA and INTR dt nodes to the latest DT bindings.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

DP connector needs to provide 3.3V on the connector's power pin. Devices
like active adapters need the power to function.

This patch enables the power with a GPIO hog, so it's always enabled as
the power needs to be enabled for us to even detect that an active
adapter is connected.

Probably the power should be enabled only if the DP driver is loaded,
and disabled on remove or suspend, but as it's not clear where the power
should be handled (it's not really part of the DP IP in any way), we use
GPIO hog for now.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Jyri Sarha <jsarha@ti.com>

Add dp0_pins_default pinmux node and setup dss, dss_ports, mhdp, and
dp0_ports nodes for DisplayPort functionality.

Signed-off-by: Jyri Sarha <jsarha@ti.com>

Add DT node for J721E virtual cpsw9g MAC device. The main_uart2
is used by eth switch fw running on remote R5F core, so it has
to be hidden from Linux.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

USB0 supports super-speed mode on the EVM. Enable that.
On the EVM, USB0 uses SERDES3 for super-speed lane.

Since USB0 is a type-C port, it needs to support lane swapping
for cable flip support. This is provided using SERDES lane
swap feature. Provide the Type-C cable orientation GPIO
to the SERDES Wrapper driver.

The Type-C compainon chip on the board needs ~133ms (tCCB_DEFAULT)
to debounce the CC lines in order to detect attach and plug
orientation and reflect the correct DIR status. [1]

We need to wait for 700ms before sampling the Type-C DIR line as
there seems to be more delay on the actual boards.

[1] http://www.ti.com/lit/ds/symlink/tusb321.pdf


Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

commit 49e19745

 upstream.

Add USB0 as otg port and USB1 as host port.

Although USB0 can be used at super-speed, limit the
speed to high-speed for now till SERDES PHY support
is added.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

J721E Common Processor Board has PCIe connectors for the 1st three PCIe
instances. Configure the three PCIe instances in RC mode and disable the
4th PCIe instance.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

Add the required 'mboxes' property to the C71x DSP processor on the TI
J721E common processor board. The mailboxes and some shared memory are
required for running the Remote Processor Messaging (RPMsg) stack between
the host processor and each of the R5Fs. The chosen sub-mailboxes match
the values used in the current firmware images. This can be changed,
if needed, as per the system integration needs after making appropriate
changes on the firmware side as well.

Signed-off-by: Suman Anna <s-anna@ti.com>

Add the required 'mboxes' property to both the C66x DSP processors on the
TI J721E common processor board. The mailboxes and some shared memory
are required for running the Remote Processor Messaging (RPMsg) stack
between the host processor and each of the R5Fs. The chosen sub-mailboxes
match the values used in the current firmware images. This can be changed,
if needed, as per the system integration needs after making appropriate
changes on the firmware side as well.

Signed-off-by: Suman Anna <s-anna@ti.com>

Add the required 'mboxes' property to all the R5F processors on the
TI J721E common processor board. The mailboxes and some shared memory
are required for running the Remote Processor Messaging (RPMsg) stack
between the host processor and each of the R5Fs. The chosen sub-mailboxes
match the values used in the current firmware images. This can be changed,
if needed, as per the system integration needs after making appropriate
changes on the firmware side as well.

Note that any R5F Core1 resources are needed and used only when that
R5F cluster is configured for Split-mode.

Signed-off-by: Suman Anna <s-anna@ti.com>

sdhci0 is connected to an eMMC and sdhci1 is connected to an SD card
slot. Add support for these nodes. Also add a gpio-regulator to power
cycle the card and one to switch I/O voltage to 1.8V.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

The TI j721e EVM base board has TI DP83867 PHY connected to external CPSW
NUSS Port 1 in rgmii-rxid mode.

Hence, add pinmux and Ethernet PHY configuration for TI j721e SoC MCU
Gigabit Ethernet two ports Switch subsystem (CPSW NUSS).
It also enables pps support for MCU CPSW CPTS by routing GenF1 output to
MCU_CPTS_HW4_PUSH input using timesync router.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

The codec is wired in multi DAI setup (DIN1/2/3/4/DOUT1/2/3 is connected to
McASP serializer).

For some reason with DIN1/DOUT1 setup we can not get 96KHz audio to work as
we would need to run REFCLK2 in 256xFS rate, but then in all sampling rates
the channel 4-7 is going to be muted :o

For other unknown reason 256xFS SCKI does not have this quirk and we can
use 96KHz as well.

There are couple of notable difference compared to DIN1/DOUT1 mode:
the channel mapping is 'random' for first look compared to the single
serializer setup.

Due to the audio setup in hardware with the generic sound card the features
we can support is limited.

With the custom audio driver it is possible to support both 48KHz and
44.1Khz sampling rate families by switching between PLL4/15 as needed.

We can also support both 16 and 24 bit audio in this case as with a custom
driver we can change the slot_width on the bus.

So the channel mapping:
        _      _      _
       |o|c1  |o|p1  |o|p3
 _     | |    | |    | |
|o|c3  |o|c2  |o|p4  |o|p2
------------------------

c1/2/3 - capture jacks (3rd is line)
p1/2/3/4 - playback jacks (4th is line)

2 channel audio (stereo):
0 (left):  p1/c1 left
1 (right): p1/c1 right

4 channel audio:
0: p1/c1 left
1: p2/c2 left
2: p1/c1 right
3: p2/c2 right

6 channel audio
0: p1/c1 left
1: p2/c2 left
2: p3/c3 left
3: p1/c1 right
4: p2/c2 right
5: p3/c3 right

8 channel audio
0: p1/c1 left
1: p2/c2 left
2: p3/c3 left
3: p4 left
4: p1/c1 right
5: p2/c2 right
6: p3/c3 right
7: p4 right

The reason is that we need to put data to all enabled serializers first.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>

Enable I2Cs, ADCs, OSPIs and UFS peripherals present on J721e.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

[ Upstream commit eb9f9173 ]

Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the J721E SoCs to the J721E common
processor board. These include the R5F remote processors in the dual-R5F
cluster (MCU_R5FSS0) in the MCU domain and the two dual-R5F clusters
(MAIN_R5FSS0 & MAIN_R5FSS1) in the MAIN domain; the two C66x DSP remote
processors and the single C71x DSP remote processor in the MAIN domain.
These sub-mailbox nodes utilize the System Mailbox clusters 0 through 4.
All the remaining mailbox clusters are currently not used on A72 core,
and so are disabled.

The sub-mailbox nodes added match the hard-coded mailbox configuration
used within the TI RTOS IPC software packages. The R5F processor
sub-systems are assumed to be running in Split mode, so a sub-mailbox
node is used by each of the R5F cores. Only the sub-mailbox node for
the first R5F core in each cluster is used in case of a Lockstep mode
for that R5F cluster.

NOTE:
The GIC_SPI interrupts to be used are dynamically allocated and managed
by the System Firmware through the ti-sci-intr irqchip driver. So, only
valid interrupts (each cluster's User 0 IRQ output) that are used by the
sub-mailbox devices are enabled. This is done to minimize the number of
NavSS Interrupt Router outputs utilized.

[s-anna@ti.com: cherry-pick commit 'eb9f9173

' from v5.5]
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Common processor board for K3 J721E platform has two push buttons
namely SW10 and SW11.
Add a gpio-keys device node to model them as input keys in Linux.
Add required pinmux nodes to set GPIO pins as input.

Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

There are 10 gpio instances inside SoC with 3 groups as below:
- Group1: main_gpio0, main_gpio2, main_gpio4, main_gpio6
- Group2: main_gpio1, main_gpio3, main_gpio5, main_gpio7
- Group3: wkup_gpio0, wkup_gpio1

Only one instance can be used in each group at a time. So use main_gpio0,
main_gpio1 and wkup_gpio0 for the current linux context and mark other
gpio nodes as disabled.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Update the power-domain cells to 2 and mark all devices as
exclusive. Main uart 0 is the debug console for processor boards
and it is used by different software entities like u-boot, atf,
linux simultaneously. So just mark main_uart0 as shared device
for common processor board.

Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

Add Support for J721E Common Processor board support.
The EVM architecture is as follows:

+------------------------------------------------------+
|   +-------------------------------------------+      |
|   |                                           |      |
|   |        Add-on Card 1 Options              |      |
|   |                                           |      |
|   +-------------------------------------------+      |
|                                                      |
|                                                      |
|                     +-------------------+            |
|                     |                   |            |
|                     |   SOM             |            |
|  +--------------+   |                   |            |
|  |              |   |                   |            |
|  |  Add-on      |   +-------------------+            |
|  |  Card 2      |                                    |    Power Supply
|  |  Options     |                                    |    |
|  |              |                                    |    |
|  +--------------+                                    | <---
+------------------------------------------------------+
                                Common Processor Board

Common Processor board is the baseboard that has most of the actual
connectors, power supply etc. A SOM (System on Module) is plugged on
to the common processor board and this contains the SoC, PMIC, DDR and
basic high speed components necessary for functionality. Add-n card
options add further functionality (such as additional Audio, Display,
networking options).

Note:
A) The minimum configuration required to boot up the board is System On
   Module(SOM) + Common Processor Board.
B) Since there is just a single SOM and Common Processor Board, we are
   maintaining common processor board as the base dts and SOM as the dtsi
   that we include. In the future as more SOM's appear, we should move
   common processor board as a dtsi and include configurations as dts.
C) All daughter cards beyond the basic boards shall be maintained as
   overlays.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>