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Lu Baolu authored
[ Upstream commit 04c00956 ]

The Scalable-mode Page-walk Coherency (SMPWC) field in the VT-d extended
capability register indicates the hardware coherency behavior on paging
structures accessed through the pasid table entry. This is ignored in
current code and using ECAP.C instead which is only valid in legacy mode.
Fix this so that paging structure updates could be manually flushed from
the cache line if hardware page walking is not snooped.

Fixes: 765b6a98

 ("iommu/vt-d: Enumerate the scalable mode capability")
Signed-off-by: default avatarLu Baolu <baolu.lu@linux.intel.com>
Cc: Ashok Raj <ashok.raj@intel.com>
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Link: https://lore.kernel.org/r/20200622231345.29722-6-baolu.lu@linux.intel.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
33104571
Forked from BeagleBoard.org / Linux
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Linux kernel
============

There are several guides for kernel developers and users. These guides can
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There are various text files in the Documentation/ subdirectory,
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Please read the Documentation/process/changes.rst file, as it contains the
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