ALSA: hda/cirrus: Add extra 10 ms delay to allow PLL settle and lock.

New HW platforms with multiple CS42L42 parts, faster CPU and i2c
requre some extra delay to allow PLL to settle and lock. Adding
extra 10ms delay.

Signed-off-by: Vitaly Rodionov <vitalyr@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20221205145713.23852-1-vitalyr@opensource.cirrus.com


Signed-off-by: Takashi Iwai <tiwai@suse.de>