- Sep 30, 2022
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Add the node for sa2ul crypto accelerator. Signed-off-by:
Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Add endpoint configuration for the four ingress and two egress threads for main domain crypto accelerator. Signed-off-by:
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Enable the TCA5608 I2C GPIO expander on main_i2c5 which provides the CSI2 expansion GPIOs on J784S4 EVM. Signed-off-by:
Vaishnav Achath <vaishnav.a@ti.com> Signed-off-by:
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The ADAS Sensor Fusion Application board can be used with J784S4 to connect up to 8 2MP cameras. Signed-off-by:
Pratyush Yadav <p.yadav@ti.com> Signed-off-by:
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CSI2RX and corresponding DPHY instances were disabled in the j784s4-main.dtsi, enable these instances. Signed-off-by:
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Enable the I2C instance and add pinmux entries for main_i2c5 which is the camera control interface for CSI. Signed-off-by:
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Add the entries for two CSI2RX instances and corresponding DPHY for J784S4 and keep them disabled by default. Signed-off-by:
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J784S4 SoC supports two PCIE instances as follows: * PCIE0 - 4x lanes * PCIE1 - 4x lanes J784S4 EVM board has the following PCIE connectors: * PCIE0 - 4x lanes * PCIE1 - 2x lanes Signed-off-by:
Matt Ranostay <mranostay@ti.com> Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by:
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The J7 Quad Port Add-On Ethernet Card for J784s4 Common-Proc-Board supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode. Add support to reset PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses directly from U-Boot. Disable cpsw9g_virt_mac node in device-tree since native ethernet driver supports CPSW2G and CPSW9G. Replace j784s4-main-r5f0_0-fw which currently points to EthFw, with: pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f which is currently unused, to ensure that EthFw is not loaded. Signed-off-by:
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Add CPSW9G virt-mac nodes required by EthFw and enable the following nodes main_udmass_inta, main_ringacc and main_udmap required for communication between EthFw and virt-mac driver. Assign SerDes lane mapping required by EthFw. EthFw will be enabled by default with these changes. Signed-off-by:
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Enable MCU CPSW2G Signed-off-by:
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Cleanup mcu_cpsw node, by deleting "status = disabled" present within the "mdio@f00", "cpts@3d000" and "phy@4040" nodes for the following reasons: - Since the outer mcu_cpsw node is disabled by default, the inner "mdio@f00" and "cpts@3d000" nodes will also be disabled. - When the mcu_cpsw node is enabled, the "mdio@f00" node is also required to be enabled by default. - The "cpts@3d000" node does not have a label, so it will not be possible to enable it selectively when the mcu_cpsw node is enabled. - The "phy@4040" node is not a device. The cleanup will make the mcu_cpsw node similar to the main_cpsw0 and main_cpsw1 nodes. Signed-off-by:
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Add CPSW2G device tree node for the main domain CPSW2G and enable it. Signed-off-by:
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Add CPSW9G nodes. Signed-off-by:
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Add DT nodes for all instances of WIZ and SERDES modules. Signed-off-by:
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The system controller node manages the CTRL_MMR0 region. Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux. Signed-off-by:
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CPSW9G in J784s4 supports modes such as QSGMII. Add a new compatible for it. Signed-off-by:
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Each of the CPSW9G ports in J784s4 supports modes such as QSGMII. Add a new compatible for it and extend the qsgmii-main-ports support for J784s4. Signed-off-by:
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Add psil thread IDs for J784s4 and include J784s4 in the set of "k3_soc_devices" in k3-psil.c. Signed-off-by:
Apurva Nandan <a-nandan@ti.com> Signed-off-by:
Hari Nagalla <hnagalla@ti.com> Signed-off-by:
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J784S4 SoC's JTAG PARTNO is 0xBB80. Signed-off-by:
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Update bindings for TI K3 J784S4 SoC which contains 9 ports (8 external ports) CPSW9G module and add compatible for it. Signed-off-by:
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TI's J784S4 SoC supports additional PHY modes like QSGMII. Add a compatible for it. Enable the use of "ti,qsgmii-main-ports" property for J784S4. Signed-off-by:
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There are 4 lanes in the single instance of J784S4 SERDES. Each SERDES lane mux can select upto 4 different IPs. Define all the possible functions. Signed-off-by:
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- Sep 28, 2022
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LCPD Auto Merger authored
TI-Feature: rpmsg TI-Branch: rpmsg-ti-linux-5.10.y-intg * 'rpmsg-ti-linux-5.10.y-intg' of git://git.ti.com/rpmsg/rpmsg : arm64: dts: ti: Enable remote procs on J784S4 EVM arm64: dts: ti: k3-j784s4-mcu: Add MCU domain R5F cluster node arm64: dts: ti: k3-j784s4-main: Add MAIN domain R5F cluster and C7x nodes Signed-off-by:
LCPD Auto Merger <lcpd_integration@list.ti.com>
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : phy: cdns-dphy: Fix common module reset logic Signed-off-by:
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Hari Nagalla authored
Enable R5F and C7x DSP device nodes and also set the IPC shared memory careveouts. These should match with the IPC and external memory sections of the remote processor FW binary. Signed-off-by: -
Hari Nagalla authored
The J784S4 SoCs have 4 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining three clusters are present in the MAIN domain (MAIN_R5FSS0, MAIN_R5FSS1 & MAIN_R5FSS2). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. The inter-processor communication between the main A72 cores and the R5F, C71x processors is achieved through shared memory and mailbox. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MCU R5FSS0 Core0: j784s4-mcu-r5f0_0-fw (both in LockStep and Split modes) MCU R5FSS0 Core1: j784s4-mcu-r5f0_1-fw (needed only in Split mode) Signed-off-by: -
Hari Nagalla authored
The J784S4 SoCs have 4 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster (MCU_R5FSS0) is present within the MCU domain, and the remaining three clusters are present in the MAIN domain (MAIN_R5FSS0, MAIN_R5FSS1 & MAIN_R5FSS2). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. And in addition there are four C7x DSP subsystems in the MAIN voltage domain. The inter-processor communication between the main A72 cores and the R5F, C71x processors is achieved through shared memory and mailbox. The following firmware names are used by default for these cores, and can be overridden in a board dts file if needed: MAIN R5FSS0 Core0: j784s4-main-r5f0_0-fw (both in LockStep and Split modes) MAIN R5FSS0 Core1: j784s4-main-r5f0_1-fw (needed only in Split mode) MAIN R5FSS1 Core0: j784s4-main-r5f1_0-fw (both in LockStep and Split modes) MAIN R5FSS1 Core1: j784s4-main-r5f1_1-fw (needed only in Split mode) MAIN R5FSS2 Core0: j784s4-main-r5f2_0-fw (both in LockStep and Split modes) MAIN R5FSS2 Core1: j784s4-main-r5f2_1-fw (needed only in Split mode) C71x_0 DSP : j784s4-c71_0-fw C71x_1 DSP : j784s4-c71_1-fw C71x_2 DSP : j784s4-c71_2-fw C71x_3 DSP : j784s4-c71_3-fw Signed-off-by: -
While inverting the logic for SoC specific common module reset, the DPHY_LANE_RESET_CMN_EN was performed only when soc_device_match() returns match, but since the newer SoCs has been removed from the table, this causes issue with streaming for newer SoCs.This commit fixes the common module reset properly to not issue software reset only for J721E SR1.0 and issue software RSTB_CMN for all other new platforms. Fixes: 0f25c348 ("phy: cdns-dphy: Update common module reset logic for newer platforms") Signed-off-by:
Jai Luthra <j-luthra@ti.com> Signed-off-by:
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : arm64: dts: ti: k3-j721e-sk-*: Add DTB overlay to enable EHRPWMs arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header arm64: dts: ti: k3-j721e-*: Add dts nodes for EHRPWMs dt-bindings: mfd: ti,j721e-system-controller: Add clock property dt-bindings: soc: ti: j721e-pat: Fix a minor syntax error Signed-off-by:
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- Sep 27, 2022
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : spi: spi-cadence-quadspi: Disable DMA due to errata id i2285 media: ti: j721e-csi2rx: Fix unused retval in set_fmt arm64: dts: ti: k3-am642-evm: Set delay values for DP83869 Tx/Rx PCI: j721e: Add support to build pci-j721e as module PCI: cadence: Add support to build pcie-cadence library as module PCI: EXPORT pci_find_host_bridge() Signed-off-by:
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Add DTB overlay to enable EHRPWM 2 and 3 and add pinmux to bring them out on RPi expansion header Signed-off-by:
Rahul T R <r-ravikumar@ti.com> Signed-off-by:
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Add pinmux required to bring out i2c5 and gpios on 40 pin RPi header on sk board Upstream Link: https://lore.kernel.org/all/20220920094713.18950-3-r-ravikumar@ti.com/ Signed-off-by:
Sinthu Raja <sinthu.raja@ti.com> Signed-off-by:
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Add dts nodes for 6 EHRPWM instances on SoC Upstream Link: https://lore.kernel.org/all/20220920094713.18950-2-r-ravikumar@ti.com/ Signed-off-by:
Vijay Pothukuchi <vijayp@ti.com> Signed-off-by:
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commit 3e26292d upstream. Add a pattern property for clock-controller, also update the example with a clock-controller node Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20220530101031.11357-2-r-ravikumar@ti.com Signed-off-by:
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Add a missing ":" after ti,pat-window-size Signed-off-by:
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- Sep 26, 2022
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Vignesh Raghavendra authored
As per errata id i2285 of AM64x Errata doc [1] BCDMA can only be used when data source and DMA descriptor source is on the same endpoint. In case of OSPI mem to mem DMA read, descriptor is in DDR while source data is in OSPI which may trigger above errata leading to read data corruption on AM64x SR1.0 devices. Therefore disable OSPI DMA on such SoCs. Subsequent SR versions are not affected. [1] https://www.ti.com/lit/er/sprz457e/sprz457e.pdf Signed-off-by:
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Fix unused retval introduced in commit 08f2542b ("media: ti: j721e-csi2rx: Add get_fmt and set_fmt pad ops") Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
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The Tx and Rx delay values affect CPSW Port 2 / ICSSG Port 1/2. This patch sets the Tx and Rx delay values as below for DP83869 in order to gain stability. Tx delay - 250ps Rx delay - 2ns Signed-off-by:
MD Danish Anwar <danishanwar@ti.com> Signed-off-by:
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Add support to build pci-j721e as module. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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