- Jul 13, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : drm/bridge: ti-sn65dsi86: Detect id panel is connected drm/bridge: ti-sn65dsi86: Return probe deffer in finding dsi host Signed-off-by:
Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
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Detect if panel is connected during bridge attach and return the status in connector detect hook. Also add pm runtime calls in the aux transfer function since this should be supported even before pre enable Signed-off-by:
Rahul T R <r-ravikumar@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Move finding dsi host to a earlier stage in the probe and return EPROBE_DEFFER in case dsi host is not probed yet Signed-off-by:
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- Jul 10, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configuration net: ethernet: ti: am65-cpsw: Fix devlink port register sequence Signed-off-by:
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commit e72659b6 upstream. This patch adds workaround for TI J721E errata i2183 (https://www.ti.com/lit/er/sprz455a/sprz455a.pdf ). PCIe fails to link up if SERDES lanes not used by PCIe are assigned to another protocol. For example, link training fails if lanes 2 and 3 are assigned to another protocol while lanes 0 and 1 are used for PCIe to form a two lane link. This failure is due to an incorrect tie-off on an internal status signal indicating electrical idle. Status signals going from SERDES to PCIe Controller are tied-off when a lane is not assigned to PCIe. Signal indicating electrical idle is incorrectly tied-off to a state that indicates non-idle. As a result, PCIe sees unused lanes to be out of electrical idle and this causes LTSSM to exit Detect.Quiet state without waiting for 12ms timeout to occur. If a receiver is not detected on the first receiver detection attempt in Detect.Active state, LTSSM goes back to Detect.Quiet and again moves forward to Detect.Active state without waiting for 12ms as required by PCIe base specification. Since wait time in Detect.Quiet is skipped, multiple receiver detect operations are performed back-to-back without allowing time for capacitance on the transmit lines to discharge. This causes subsequent receiver detection to always fail even if a receiver gets connected eventually. The workaround only works for 1-lane PCIe configuration. This workaround involves enabling receiver detect override by setting TX_RCVDET_OVRD_PREG_j register of the lane running PCIe to 0x2. This causes SERDES to indicate successful receiver detect when LTSSM is in Detect.Active state, whether a receiver is actually present or not. If the receiver is present, LTSSM proceeds to link up as expected. However if receiver is not present, LTSSM will time out in Polling.Configuration substate since the expected training sequence packets will not be received. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20220303055026.24899-1-sjakhade@cadence.com Signed-off-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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Renaming interfaces using udevd depends on the interface being registered before its netdev is registered. Otherwise, udevd reads an empty phys_port_name value, resulting in the interface not being renamed. Fix this by registering the interface before registering its netdev by invoking am65_cpsw_nuss_register_devlink() before invoking register_netdev() for the interface. Move the function call to devlink_port_type_eth_set(), invoking it after register_netdev() is invoked, to ensure that netlink notification for the port state change is generated after the netdev is completely initialized. Fixes: 4c3e6208 ("net: ti: am65-cpsw-nuss: Add devlink support") Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by:
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- Jul 07, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : net: ethernet: ti: am65-cpsw: Fix build error without PHYLINK ti_config_fragments: connectivity: Enable GPIO bitbang MDIO Signed-off-by:
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commit bfa323c6 upstream. If PHYLINK is n, build fails: drivers/net/ethernet/ti/am65-cpsw-ethtool.o: In function `am65_cpsw_set_link_ksettings': am65-cpsw-ethtool.c:(.text+0x118): undefined reference to `phylink_ethtool_ksettings_set' drivers/net/ethernet/ti/am65-cpsw-ethtool.o: In function `am65_cpsw_get_link_ksettings': am65-cpsw-ethtool.c:(.text+0x138): undefined reference to `phylink_ethtool_ksettings_get' drivers/net/ethernet/ti/am65-cpsw-ethtool.o: In function `am65_cpsw_set_eee': am65-cpsw-ethtool.c:(.text+0x158): undefined reference to `phylink_ethtool_set_eee' Select PHYLINK for TI_K3_AM65_CPSW_NUSS to fix this. Fixes: e8609e69 ("net: ethernet: ti: am65-cpsw: Convert to PHYLINK") Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Reviewed-by:
Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/20220409105931.9080-1-yuehaibing@huawei.com Signed-off-by:
Jakub Kicinski <kuba@kernel.org> Signed-off-by:
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Lets enable GPIO bitbang MDIO support for some of the platforms that can benefit out of it Suggested-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
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- Jun 28, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : net: ethernet: ti: am65-cpsw: Add RMII mode to supported interfaces Signed-off-by:
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Support for RMII mode is already present in the am65-cpsw driver. Currently, RMII mode is not set as a supported phy_mode in struct "phylink_config"'s supported_interfaces member. This prevents an interface from being used in RMII mode. Fix it by adding RMII mode as a supported phy-mode if requested by the interface. Signed-off-by:
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Texas Instruments Auto Merger authored
TI-Feature: platform_base TI-Branch: platform-ti-linux-5.10.y * 'platform-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform : dmaengine: ti: k3-psil: add additional TX threads for j7200 dmaengine: ti: k3-psil: add additional TX threads for j721e arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator dmaengine: ti: k3-psil-j721s2: Add psil threads for sa2ul arm64: dts: ti: k3-am62-main: Do not exclusively claim SA3UL arm64: dts: ti: k3-am64-main: Do not exclusively claim SA2UL arm64: dts: ti: k3-am65-main: Do not exclusively claim SA2UL arm64: dts: ti: k3-am65-main: Move SA2UL to unused PSI-L thread ID arm64: dts: ti: k3-am62-main: Disable RNG node arm64: dts: ti: k3-am64-main: Disable RNG node arm64: dts: ti: k3-j7200-mcu-wakeup: Disable RNG node arm64: dts: ti: k3-am65-main: Disable RNG node crypto: sa2ul - Check engine status before enabling misc: Kconfig: add DMABUF_HEAPS dependency to SRAM_DMA_HEAP gpio: davinci: Add support for system suspend/resume PM Signed-off-by:
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- Jun 27, 2022
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Matt Ranostay authored
Add matching PSI-L threads mapping for transmission DMA channels on the J7200 platform. Signed-off-by:Matt Ranostay <mranostay@ti.com>
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Matt Ranostay authored
Add matching PSI-L threads mapping for transmission DMA channels on the J721E platform. Signed-off-by: -
Jayesh Choudhary authored
Add the node for SA2UL for supporting hardware crypto algorithms, including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites. Signed-off-by:Jayesh Choudhary <j-choudhary@ti.com>
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Jayesh Choudhary authored
Add endpoint configuration for the four ingress and two egress threads for main domain crypto accelerator. Signed-off-by:
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- Jun 25, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : net: ti: icssg_prueth: support larger MTU of upto 1982 bytes arm64: dts: ti: k3-j721s2-common-proc-board: Add DP1 arm64: dts: ti: k3-j721s2-som-p0: add DSI to eDP arm64: dts: ti: k3-j721s2-main: add DSI & DSI PHY drm: bridge: cdns-mhdp8546: Fix bridge attach for no-hpd case drm/panel: simple: Add an eDP panel dt-bindings: display: simple: Add simple TI edp panel drm/bridge: ti-sn65dsi86: Add necessary dsi flags drm/bridge: ti-sn65dsi86: Disable ASSR drm/bridge: ti-sn65dsi86: Move DSI attach to probe drm/bridge: ti-sn65dsi86: Fix warning in pm ops ti_config_fragments: audio_display: Enable DSI bridge phy: cdns-dphy: Add support for DPHY TX on J721e phy: cdns-dphy: Add band config for dphy tx drm/bridge: cdns-dsi: Add support for J721E wrapper drm/bridge: cdns-dsi: Create a header file drm/bridge: cdns-dsi: Move to drm/bridge/cadence drm/bridge: cdns-dsi: Add support for pre_enable and post_enable control functions. drm/tidss: Soft Reset DISPC on startup Signed-off-by:
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MII_G port defaults are 2000 bytes. (i.e. MII_G_RT_RX_STAT_MAX_SIZE_PRU0/1 & MII_G_RT_TX_STAT_MAX_SIZE_PORT0/1) Removing 14 bytes of Ethernet MAC header and 4 bytes of FCS we are left with a payload size (MTU) of 1982. Update MII_RT_RX_FRMS0/1 to the same (2000-1) and set max MTU of the PRU Ethernet device driver to 1982. Signed-off-by:
Roger Quadros <rogerq@kernel.org> Signed-off-by:
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Add the endpoint nodes to describe connection from DSS => DSI Bridge => DSI to eDP bridge => eDP panel. Signed-off-by:
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Add DT nodes for DSI to eDP bridge. The DSI to edp bridge is sn65dsi86 on SOM Signed-off-by:
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Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper. Signed-off-by:
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Currently bridge attach failed when display not connected. Right thing to do is to mark the connector as not connected and return success to bridge attach. Fix this by returning 0 in bridge attach Fixes: 8e20b40c ("drm: bridge: cdns-mhdp8546: Add support for no-hpd") Signed-off-by:
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Add a simple eDP panel for attaching dsi2edp bridge. Generic eDP panel is already there in upstream, backporting that was difficult since upstream has moved a lot compared to SDK Signed-off-by:
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Add compatible for TI edp panel Signed-off-by:
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Enable EOT and SYNC pulse flags to dsi which are neccessry, and make dsi as 2 lanes Signed-off-by:
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Disable ASSR Display authentication, since ASSR is only supported in eDP and not supported in DP. So disabling ASSR to support both DP and eDP Signed-off-by:
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Move DSI attach to probe since the upstreame bridge is created in the dsi attach and this is needed for DSS probing to happen Signed-off-by:
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gpio_set_value triggered below warning WARNING: CPU: 1 PID: 244 at drivers/gpio/gpiolib.c:3119 gpiod_set_value+0x5c/0x68 Fix this by using gpiod_set_value_cansleep Signed-off-by:
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Enable CDNS DSI bridge module Signed-off-by:
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Add support for dphy-tx on j721e by implement dphy ops required. Upstream Link: https://lore.kernel.org/all/20220622075340.16915-4-r-ravikumar@ti.com/ Signed-off-by:
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Add support for band ctrl config for dphy tx. Upstream Link: https://lore.kernel.org/all/20220622075340.16915-3-r-ravikumar@ti.com/ Signed-off-by:
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Add support for wrapper settings for DSI bridge on j721e. Also set the DPI input to DPI0 Upstream Link: https://lore.kernel.org/all/20220620205403.31744-5-r-ravikumar@ti.com/ Signed-off-by:
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Create a header file for cdns dsi and move register offsets and structure to header, to prepare for adding j721e wrapper support Upstream Link: https://lore.kernel.org/all/20220620205403.31744-4-r-ravikumar@ti.com/ Signed-off-by:
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Move the cadence dsi bridge under drm/bridge/cadence directory, to prepare for adding j721e wrapper support Upstream Link: https://lore.kernel.org/all/20220620205403.31744-3-r-ravikumar@ti.com/ Signed-off-by:
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commit aebeb02d upstream Add support for pre_enable and post_enable drm bridge control functions. Making sure that host to be prepared before panel is powered up, for the panels like TC358762. Signed-off-by:
Jayshri Pawar <jpawar@cadence.com> Reviewed-by:
Robert Foss <robert.foss@linaro.org> Signed-off-by:
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commit c9b2d923 upstream. Soft reset the display subsystem controller on startup and wait for the reset to complete. This helps the scenario where display was already in use by some other core before the linux was booted. Signed-off-by:
Devarsh Thakkar <devarsht@ti.com> Signed-off-by:
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- Jun 24, 2022
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Andrew Davis authored
The SA3UL hardware is also used by SYSFW and OP-TEE. It should be requested using the shared TI-SCI flags instead of the exclusive flags or the request will fail. Signed-off-by:
Andrew Davis <afd@ti.com> [praneeth@ti.com: minor edit in commitmsg] Signed-off-by:
Praneeth Bajjuri <praneeth@ti.com>
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Andrew Davis authored
The SA2UL hardware is also used by SYSFW and OP-TEE. It should be requested using the shared TI-SCI flags instead of the exclusive flags or the request will fail. Signed-off-by: -
Andrew Davis authored
The SA2UL hardware is also used by SYSFW and OP-TEE. It should be requested using the shared TI-SCI flags instead of the exclusive flags or the request will fail. Signed-off-by: -
Andrew Davis authored
The first TX and first two RX PSI-L threads for SA2UL are used by SYSFW on High Security(HS) devices. Use the next available threads to prevent resource allocation conflicts. Signed-off-by:
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