- Nov 18, 2022
-
-
Robert Nelson authored
Reference: v5.15.77 Signed-off-by:Robert Nelson <robertcnelson@gmail.com>
-
Robert Nelson authored
Reference: v5.10.154 Signed-off-by: -
-
-
Robert Nelson authored
Signed-off-by: -
-
Robert Nelson authored
Signed-off-by: -
-
Jason Kridner authoredFrom https://github.com/statropy/wpanusb
-
-
Robert Nelson authored
Signed-off-by: -
-
Robert Nelson authored
Signed-off-by: -
Robert Nelson authored
Signed-off-by: -
Robert Nelson authored
Signed-off-by: -
Robert Nelson authored
Signed-off-by: -
Prashanth Kumar Amai authored
v4l:vxd-dec:Flushing all the IO buffers and releasing all the held buffers while joing v4l2 job_abort. This patch does the fulsh operation by releasing all the locked up buffers in the driver. It throws the v4l2 harmless traces while trying to re-release the released buffers. Signed-off-by:Prashanth Kumar Amai <prashanth.amai@ti.com>
-
Keerthy authored
Signed-off-by:Keerthy <j-keerthy@ti.com>
-
Lucas Weaver authored
Confine the memory map changes into a separate rtos-memory-map.dts which describes the common memory map for all RTOS remoteprocs. vision-apps.dtbo uses this and also disables capture and display related peripherals from Linux so that it can be used by RTOS. edgeai-apps.dtbo expects these devices to be owned by linux, so it uses the rtos-memory-map customization only. Signed-off-by:Nikhil Devshatwar <nikhil.nd@ti.com>
-
- Oct 28, 2022
-
-
LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : PCI: j721e: correct PCIe lane selection mask net: ethernet: ti: am65-cpsw: set correct devlink flavour for unused ports Signed-off-by:
LCPD Auto Merger <lcpd_integration@list.ti.com>
-
LCPD Auto Merger authored
TI-Feature: platform_base TI-Branch: platform-ti-linux-5.10.y * 'platform-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform : arm64: dts: ti: k3-j721s2: Fix the interrupt ranges property for main & wkup gpio intr Signed-off-by:
-
- Oct 27, 2022
-
-
Keerthy authored
The parent's input irq number is wrongly subtracted with 32 instead of using the exact numbers in: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j721s2/interrupt_cfg.html The GPIO interrupts are not working because of that. The toggling works fine but interrupts are not firing. Fix the parent's input irq that specifies the base for parent irq. Tested for MAIN_GPIO0_6 interrupt on the j721s2 EVM. Signed-off-by:
-
LCPD Auto Merger authored
TI-Feature: rpmsg TI-Branch: rpmsg-ti-linux-5.10.y-intg * 'rpmsg-ti-linux-5.10.y-intg' of git://git.ti.com/rpmsg/rpmsg : arm4: dts: ti: Reduce reserved area for R5F by 1Mb Signed-off-by:
-
PCIe lane mask should be based on the maximum number of lanes and not the currently selected lane count, since we have no idea what the bootloader may have initialized to this register. Reported-by:
Vignesh Raghavendra <vigneshr@ti.com> Fixes: 3c97d831 ("PCI: j721e: correct lane count mask based on lane numbers") Signed-off-by:
Matt Ranostay <mranostay@ti.com> Signed-off-by:
-
commit 7e777b1b upstream. am65_cpsw_nuss_register_ndevs() skips calling devlink_port_type_eth_set() for ports without assigned netdev, triggering the following warning when DEVLINK_PORT_TYPE_WARN_TIMEOUT elapses after 3600s: Type was not set for devlink port. WARNING: CPU: 0 PID: 129 at net/core/devlink.c:8095 devlink_port_type_warn+0x18/0x30 Fixes: 3e8e73d1 ("net: ethernet: ti: am65-cpsw: Fix devlink port register sequence") Signed-off-by:
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
David S. Miller <davem@davemloft.net> Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by:
-
Devarsh Thakkar authored
In the previous version of devicetree, reserved area for wakeup R5F was stating from 0x9db00000, so to provide compatibility with older version of devicetree being used with new wakeup R5F firmware, the wakeup R5F reserved area is reduced by 1Mb and that 1Mb is moved to MCU M4F reserved area. Signed-off-by:Devarsh Thakkar <devarsht@ti.com>
-
- Oct 25, 2022
-
-
LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : spi: spi-omap2-mcspi: Use EOW interrupt for completion when DMA enabled dmaengine: ti: k3-udma: Respond TX done if DMA_PREP_INTERRUPT is not requested arm64: dts: ti: k3-j784s4-evm: Add eMMC mmc0 support arm64: dts: ti: k3-j784s4-evm: Add OSPI0 flash support Signed-off-by:
-
- Oct 21, 2022
-
-
LCPD Auto Merger authored
TI-Feature: platform_base TI-Branch: platform-ti-linux-5.10.y * 'platform-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform : ti_config_fragments: v8_audio_display: Trim out defaults ti_config_fragments: audio_display: Move option pruning into prune.cfg ti_config_fragments: Clone audio_display.cfg for ARMv8 ti_config_fragments: v8_baseport: Trim out defaults ti_config_fragments: baseport: Trim out defaults ti_config_fragments: baseport: Move option pruning into prune.cfg ti_config_fragments: real_time: Remove explicit page size setting Signed-off-by:
-
Andrew Davis authored
With the same justification as the previous patches in this series. Move option pruning into the prune.cfg file and remove the remaining option additions that do not change defaults. Signed-off-by:Andrew Davis <afd@ti.com>
-
Andrew Davis authored
While pruning is useful for making small and fast-building kernels for our SDK releases, these are not so useful for general purpose or distro kernels where these options might still be needed. Move all the pruning from audio_display.cfg into multi_v7_prune.cfg. Signed-off-by: -
Andrew Davis authored
The one audio_display.cfg is used in both v7 and v8 maps. This prevents more fine-grain pruning. For example v8 does not need OMAPDRM, but we cannot remove it without removing it also from v7. Make a clone of audio_display.cfg for use in the v8 map. Signed-off-by: -
Andrew Davis authored
All carried changes to the upstream kernel that are needed to boot it on TI platforms should be considered tech debt. Changes to the default ARMv8 configuration are no different. We need to reduced these over time by working to get these options in the upstream defconfig. To start to see where we stand today, lets remove all the options that do not change the upstream default. Then anything remaining in this file should be investigated for appropriateness in upstream and sent accordingly. Signed-off-by: -
Andrew Davis authored
All carried changes to the upstream kernel that are needed to boot it on TI platforms should be considered tech debt. Changes to the default ARMv8 configuration are no different. We need to reduced these over time by working to get these options in the upstream defconfig. To start to see where we stand today, lets remove all the options that do not change the upstream default. Then anything remaining in this file should be investigated for appropriateness in upstream and sent accordingly. Signed-off-by: -
Andrew Davis authored
While pruning is useful for making small and fast-building kernels for our SDK releases, these are not so useful for general purpose or distro kernels where these options might still be needed. For these cases one would only want to apply our additions to gain support for our platforms but not trim out support for others. To make this separation clean, move all the pruning from baseport.cfg into multi_v7_prune.cfg. Signed-off-by: -
Andrew Davis authored
4K pages are now the default, no need to explicitly set the same. Signed-off-by:
-
- Oct 18, 2022
-
-
LCPD Auto Merger authored
TI-Feature: platform_base TI-Branch: platform-ti-linux-5.10.y * 'platform-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform : dmaengine: k3-udma: Add system suspend/resume support arm64: dts: ti: k3-j784s4-*: Add GPU node arm64: dts: ti: Add support for AM62A7-SK arm64: dts: ti: Introduce AM62A7 family of SoCs dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62A dt-bindings: arm: ti: Add bindings for AM62A7 SoC dt-bindings: arm: ti: Rearrange IOPAD macros alphabetically Signed-off-by:
-
Vignesh Raghavendra authored
The K3 platforms configure the DMA resources with the help of the TI's System Firmware's Device Manager(DM) over TISCI. The group of DMA related Resource Manager[1] TISCI messages includes: INTA, RINGACC, UDMAP, and PSI-L. This configuration however, does not persist in the DM after leaving from Suspend-to-RAM state. We have to restore the DMA channel configuration over TISCI for all configured channels when entering suspend. The TISCI resource management calls for each DMA type (UDMA, PKTDMA, BCDMA) happen in device_free_chan_resources() and device_alloc_chan_resources(). In pm_suspend() we store the current udma_chan_config for channels that still have attached clients and call device_free_chan_resources(). In pm_resume() restore the udma_channel_config from backup and call device_alloc_chan_resources() for those channels. Drivers like CPSW do their own DMA resource management, so use the late system suspend/resume hooks. [1] https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/index.html#resource-management-rm Signed-off-by:
Georgi Vlaev <g-vlaev@ti.com>
-
Randolph Sapp authored
Add GPU node for J784S4 SoC and enable it in the k3-j784s4-evm.dtb. This is the same IMG BXS-4-64 core used in J721S2, so it shares the same compatible value and power domain names. Signed-off-by:
Randolph Sapp <rs@ti.com> Acked-by:
-
Vignesh Raghavendra authored
commit 38c4a08c upstream. AM62A StarterKit (SK) board is a low cost, small form factor board designed for TI's AM62A7 SoC. It supports the following interfaces: * 2 GB LPDDR4 RAM * x1 Gigabit Ethernet interface * x1 HDMI Port with audio * x1 Headphone Jack * x1 USB2.0 Hub with two Type A host and x1 USB Type-C DRP Port * x1 UHS-1 capable µSD card slot * M.2 SDIO Wifi + UART slot * 1Gb OSPI NAND flash * x4 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin User Expansion Connector * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 20-pin header for Programmable Realtime Unit (PRU) IO pins * 40-pin CSI header Add basic support for AM62A7-SK. Schematics: https://www.ti.com/lit/zip/sprr459 Co-developed-by:
Bryan Brattlof <bb@ti.com> Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220901141328.899100-6-vigneshr@ti.com Signed-off-by:
-
Vignesh Raghavendra authored
commit 5fc6b1b6 upstream. The AM62A SoC belongs to the K3 Multicore SoC architecture platform that can run edge AI applications with Video/Vision processing. This provides advanced system integration with high security support to enable a broad set of applications in industrial/automotive markets such as, driver monitoring, machine vision, smart camera, eMirror, front camera, robotics, and building automation. Some highlights of AM62A SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortex-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * One AI accelerator (up to 2 TOPS), using one C7x256V DSP w/Matrix Multiplier accelerator (MMA) for Deep Learning usage. * VPAC3L(Vision Pre-processing Accelerator), providing 12-bit ISP up to 315MPixel/s RGB+IR support, and Noise Filter for improved integrated imaging and vision image processing. * H.264/H.265 Video Encode/Decode. + Motion JPEG encode * Display support, providing 24-bit RBG parallel interface up to 200MHz pixel clock support for 2K display resolution. * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3x McASP for audio, 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment * One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design. More details about the SoCs can be found in the Technical Reference Manual: https://www.ti.com/lit/zip/spruj16 Co-developed-by:
-
