- Aug 10, 2022
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When multiple serdes instances are initialized the first will succeed but additional will conflict over clocks names and probing fails. Signed-off-by:
Matt Ranostay <mranostay@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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- Aug 04, 2022
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commit b26ff913 upstream Rename ili251x_hardware_reset() to ili210x_hardware_reset(), change its parameter from struct device * to struct gpio_desc *, and use it as one single consistent reset implementation all over the driver. Also increase the minimum reset duration to 12ms, to make sure the reset is really within the spec. Signed-off-by:
Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20220518210423.106555-1-marex@denx.de Signed-off-by:
Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by:
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commit 27931d38 upstream Modern devices may redraw display at 60 Hz, make sure we have one input sample per one frame. Reduce sample period to 15ms, so we would get up to 66.6 samples per second, although realistically with all the jitter and extra scheduling wiggle room, we would end up just above 60 samples per second. This should be a good compromise between sampling too often and sampling too seldom. Signed-off-by:
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commit 8639e042 upstream Currently the ili210x driver implements a threaded interrupt handler which starts upon edge on the interrupt line, and then polls the touch controller for samples. Every time a sample is obtained from the controller, the thread function checks whether further polling is required, and if so, waits fixed amount of time before polling for next sample. The delay between consecutive samples can thus vary greatly, because the I2C transfer required to retrieve the sample from the controller takes different amount of time on different platforms. Furthermore, different models of the touch controllers supported by this driver require different delays during retrieval of samples too. Instead of waiting fixed amount of time before polling for next sample, determine how much time passed since the beginning of sampling cycle and then wait only the remaining amount of time within the sampling cycle. This makes the driver deliver samples with equal spacing between them. Signed-off-by:
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commit de889108 upstream The ili251x touch controller needs 5ms delay between sending I2C device address and register address, and, writing or reading register data. According to downstream ili251x example code, this 5ms delay is not required when reading touch samples out of the controller. Implement such a special case. Signed-off-by:
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commit c6ac8f0b upstream The ili251x firmware can be updated, this is used when switching between different modes of operation of the touch surface, e.g. glove operation. This patch implements the firmware update mechanism triggered by a write into an sysfs attribute. The firmware itself is distributed as an intel hex file with non-standard types. The first two lines are of type 0xad, which indicates the start of DataFlash payload, that is always at address 0xf000 on the ili251x, so it can be dropped, and 0xac which indicates the position of firmware info in the Application payload, that is always at address 0x2020 on the ili251x and we do not care. The rest of the firmware is data of type 0x00, and we care about that. To convert the firmware hex file into something usable by the kernel, remove the first two lines and then use ihex2fw: $ tail -n +3 input.hex > temp.hex $ ./tools/firmware/ihex2fw temp.hex firmware/ilitek/ili251x.bin To trigger the firmware update, place firmware file ilitek/ili251x.bin into /lib/firmware/, write into firmware_update sysfs attribute and wait about 30-40 seconds. The firmware update is slow. Afterward, verify the firmware_version and mode sysfs attributes to check whether the firmware got updated and the controller switched back to application (AP) mode by reading out 'mode' attribute in sysfs. Note that the content of firmware_version, e.g. 0600.0005.abcd.aa04 can be matched to the content of the firmware hex file. The first four bytes, 0x06 0x00 0x00 0x05 can be found at ^:102030 00 05000006, the next four bytes 0xab 0xcd 0xaa 0x04 at ^:10F000 00 nnnnnnnn ABCDAA04. Note that the protocol differs considerably between the ili2xxx devices, this patch therefore implements this functionality only for ili251x that I can test. Signed-off-by:
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commit 70a7681d upstream The ili251x firmware protocol permits readout of firmware version, protocol version, mcu version and current mode (application, boot loader, forced update). These information are useful when updating the firmware on the il251x, e.g. to avoid updating the same firmware into the device multiple times. The locking is now necessary to avoid races between interrupt handler and the sysfs readouts. Note that the protocol differs considerably between the ili2xxx devices, this patch therefore implements this functionality only for ili251x that I can test. Signed-off-by:
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commit 235300ed upstream The ili251x firmware protocol permits readout of panel resolution, implement this, but make it possible to override this value using DT bindings. This way, older DTs which contain touchscreen-size-x and touchscreen-size-y properties will behave just like before and new DTs may avoid specifying these for ILI251x. Note that the command format is different on other controllers, so this functionality is isolated to ILI251x. Signed-off-by:
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Add support for the DSS IP on TI's new AM625 SoC in the tidss driver. Signed-off-by:
Aradhya Bhatia <a-bhatia1@ti.com> Reviewed-by:
Rahul T R <r-ravikumar@ti.com> Signed-off-by:
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Add ti,am625-dss compatible string. The DSS IP on TI's AM625 SoC is an update from the DSS on TI's AM65X SoC. The former has an additional OLDI TX to enable a 2K resolution on OLDI displays or enable 2 duplicated displays with a smaller resolution. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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- Jul 31, 2022
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The SERDES in SR1.0 supports 2 reference clocks. The second reference clock (core_ref1_clk) is hardwired to MAIN_PLL3_HSDIV4_CLKOUT (100/125/156.25 MHz). DM firmware update is required to set this clock to 156.25MHz for USXGMII support. Switch the SERDES wrapper device compatible to "ti,j7200-wiz-10g" to be aware of the additional reference clock and the special SCM register to manage the configuration i.e. "ti,scm" property. Switch the SERDES device compatible to "ti,j7200-serdes-10g" to support dual reference clock configurations. The SERDES clock configuration is not changed in this patch. Both the PLL reference clocks are still set to 100MHz (core_ref_clk) i.e. MAIN_PLL2_HSDIV4_CLKOUT. Later, when USXGMII is required the respective PLL reference clock can be switched to (core_ref1_clk) i.e. 156.25MHz while leaving the other PLL at 100MHz so PCIe/SGMII can continue to work. Signed-off-by:Roger Quadros <rogerq@kernel.org> Signed-off-by: Vignesh Rag...
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SR2.0 has some differences than SR1.0. The current DT files will contain SR2.0 material and all SR1.0 specific differences will be held in these new overlay files. The usage model is same as in AM65. Silicon specific changes should be in DT overlay: k3-j7200-sr1.dts The SR1.0 specific board should include the above DT overlay file and then make any board specific changes if required. e.g.: k3-j7200-common-proc-board-sr1.dts SR2.0 specific changes in main device tree files will be added later. Signed-off-by:
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Add a separate compatible and registers map table for TI J7200. TI J7200 uses Torrent SD0805 version which is a special version derived from SD0801 that has two internal reference clocks along with one external reference clock. Add register sequences for USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink config for TI J7200. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by:
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Add compatible for "ti,j7200-serdes-10g". The PHY module can take 2 reference clocks so add provision for that. Signed-off-by:
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For J7200-SR2.0 and AM64 we don't model Common refclock divider as a clock divider as the divisor rate is fixed based on operating reference clock frequency. We just program the recommended value into the register. This simplifies the device tree and implementation a lot. Signed-off-by:
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Add register sequences for USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink configuration. Signed-off-by:
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Add support for dual reference clock multilink configurations. Add register sequences for PCIe(100MHz) + USXGMII(156.25MHz) multilink configuration. Signed-off-by:
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Instead of a 3D matrix use a key:value pair table for link_cmn_vals, xcvr_diag_vals, pcs_cmn_vals, phy_pma_cmn_vals, cmn_vals, tx_ln_vals and rx_ln_vals. This makes it scaleable for multiple reference clocks. Wherever both CDNS and TI use the same settings, reuse the same data. Introduce CLK_ANY and ANY_SSC enums which are used if the setting is independent of clock rate or SSC type. Signed-off-by:
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j7200-wiz-10g supports 2 reference clocks. However, the control bits for these clocks is in a separate register that sits in the System Control register space. Handle that register. Signed-off-by:
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ti,j7200-wiz-10g supports an additional reference clock. Add compatible and the additional clock. Signed-off-by:
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Mark "pll[0|1]-refclk", "refclk-dig" and "cmn-refclk1?-dig-div" as deprecated. The clock muxes are provided by the device driver so not required in device tree. Signed-off-by:
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Changes the wiz_p_mac_div_sel() and wiz_mode_select() to configure serdes for USXGMII. Adds the support to configure mac_src_sel, refclk_sel and rxfclk_sel in the LANECTL register and configures the serdes for usxgmii. [rogerq] Fix MAC_SRC_SEL to 0x3 for USXGMII as per CSL code. Signed-off-by:
Tanmay Patil <t-patil@ti.com> Signed-off-by:
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XAUI and USXGMII PHY modes are supported via XFI mode setting in the control register. Signed-off-by:
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Add register sequences for single link USXGMII configuration supporting 156.25MHz reference clock frequency. Signed-off-by:
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Add definition for USXGMII phy type. Signed-off-by:
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- Jul 22, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : HACK: ti_config_fragments: audio_display: Bump up CMA size support Multimedia net: ethernet: ti: am65-debugfs: Fix kernel crash if CONFIG_DEBUG_FS is not set in .config arm64: dts: ti: k3-j7200: Fix MDIO clock Signed-off-by:
Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
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After testing Multi channel test cases on 4K pages it was discovered the 144MB still was not enough. Increasing it further to 512MB to align with 8.2 state and tested Multimedia testcases to be working fine. Signed-off-by:
Prasanth Babu Mantena <p-mantena@ti.com> Signed-off-by:
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Kernel boot crashes if CONFIG_DEBUG_FS is not set in .config. The cpsw-nuss driver does not handle this case. Fix the issue by implementing empty debugfs APIs Signed-off-by:
Ravi Gunasekaran <r-gunasekaran@ti.com> Signed-off-by:
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cpsw5g_mdio clock is incorrect. Fix it. Fixes: 008a8d71 ("arm64: dts: ti: k3-j7200: Add CPSW5G nodes") Signed-off-by:
Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by:
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- Jul 14, 2022
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Texas Instruments Auto Merger authored
TI-Feature: platform_base TI-Branch: platform-ti-linux-5.10.y * 'platform-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform : arm64: dts: ti: k3-am642: Fix the L2 cache sets Signed-off-by:
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Nishanth Menon authored
A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 256KB of L2 / 64 (line length) = 4096 ways 4096 ways / 16 = 256 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en [2] https://www.ti.com/lit/pdf/spruim2 Fixes: 8abae938 ("arm64: dts: ti: Add support for AM642 SoC") Reported-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
Nishanth Menon <nm@ti.com> Reviewed-by:
Pratyush Yadav <p.yadav@ti.com> Signed-off-by:
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- Jul 13, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : drm/bridge: ti-sn65dsi86: Detect id panel is connected drm/bridge: ti-sn65dsi86: Return probe deffer in finding dsi host Signed-off-by:
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Detect if panel is connected during bridge attach and return the status in connector detect hook. Also add pm runtime calls in the aux transfer function since this should be supported even before pre enable Signed-off-by:
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Move finding dsi host to a earlier stage in the probe and return EPROBE_DEFFER in case dsi host is not probed yet Signed-off-by:
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- Jul 10, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configuration net: ethernet: ti: am65-cpsw: Fix devlink port register sequence Signed-off-by:
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commit e72659b6 upstream. This patch adds workaround for TI J721E errata i2183 (https://www.ti.com/lit/er/sprz455a/sprz455a.pdf ). PCIe fails to link up if SERDES lanes not used by PCIe are assigned to another protocol. For example, link training fails if lanes 2 and 3 are assigned to another protocol while lanes 0 and 1 are used for PCIe to form a two lane link. This failure is due to an incorrect tie-off on an internal status signal indicating electrical idle. Status signals going from SERDES to PCIe Controller are tied-off when a lane is not assigned to PCIe. Signal indicating electrical idle is incorrectly tied-off to a state that indicates non-idle. As a result, PCIe sees unused lanes to be out of electrical idle and this causes LTSSM to exit Detect.Quiet state without waiting for 12ms timeout to occur. If a receiver is not detected on the first receiver detection attempt in Detect.Active state, LTSSM goes back to Detect.Quiet and again moves forward to Detect.Active state without waiting for 12ms as required by PCIe base specification. Since wait time in Detect.Quiet is skipped, multiple receiver detect operations are performed back-to-back without allowing time for capacitance on the transmit lines to discharge. This causes subsequent receiver detection to always fail even if a receiver gets connected eventually. The workaround only works for 1-lane PCIe configuration. This workaround involves enabling receiver detect override by setting TX_RCVDET_OVRD_PREG_j register of the lane running PCIe to 0x2. This causes SERDES to indicate successful receiver detect when LTSSM is in Detect.Active state, whether a receiver is actually present or not. If the receiver is present, LTSSM proceeds to link up as expected. However if receiver is not present, LTSSM will time out in Polling.Configuration substate since the expected training sequence packets will not be received. Signed-off-by:
Vinod Koul <vkoul@kernel.org> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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Renaming interfaces using udevd depends on the interface being registered before its netdev is registered. Otherwise, udevd reads an empty phys_port_name value, resulting in the interface not being renamed. Fix this by registering the interface before registering its netdev by invoking am65_cpsw_nuss_register_devlink() before invoking register_netdev() for the interface. Move the function call to devlink_port_type_eth_set(), invoking it after register_netdev() is invoked, to ensure that netlink notification for the port state change is generated after the netdev is completely initialized. Fixes: 4c3e6208 ("net: ti: am65-cpsw-nuss: Add devlink support") Signed-off-by:
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- Jul 07, 2022
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Texas Instruments Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.10.y * 'connectivity-ti-linux-5.10.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : net: ethernet: ti: am65-cpsw: Fix build error without PHYLINK ti_config_fragments: connectivity: Enable GPIO bitbang MDIO Signed-off-by:
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commit bfa323c6 upstream. If PHYLINK is n, build fails: drivers/net/ethernet/ti/am65-cpsw-ethtool.o: In function `am65_cpsw_set_link_ksettings': am65-cpsw-ethtool.c:(.text+0x118): undefined reference to `phylink_ethtool_ksettings_set' drivers/net/ethernet/ti/am65-cpsw-ethtool.o: In function `am65_cpsw_get_link_ksettings': am65-cpsw-ethtool.c:(.text+0x138): undefined reference to `phylink_ethtool_ksettings_get' drivers/net/ethernet/ti/am65-cpsw-ethtool.o: In function `am65_cpsw_set_eee': am65-cpsw-ethtool.c:(.text+0x158): undefined reference to `phylink_ethtool_set_eee' Select PHYLINK for TI_K3_AM65_CPSW_NUSS to fix this. Fixes: e8609e69 ("net: ethernet: ti: am65-cpsw: Convert to PHYLINK") Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Reviewed-by:
Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://lore.kernel.org/r/20220409105931.9080-1-yuehaibing@huawei.com Signed-off-by:
Jakub Kicinski <kuba@kernel.org> Signed-off-by:
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Lets enable GPIO bitbang MDIO support for some of the platforms that can benefit out of it Suggested-by:
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