- Feb 18, 2021
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.4.y * 'connectivity-ti-linux-5.4.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : ti_config_fragments/audio_display.cfg: Enable TI_CSI2RX HACK: media: ti-vpe: csi2rx: Drain DMA when stopping stream media: cadence: csi2rx: Turn subdev power on before starting stream arm64: dts: ti: k3-j721e: Add nodes to enable CSI2 dmaengine: ti: k3-psil-j721e: Add entry for CSI2RX media: ti-vpe: csi2rx: Add CSI2RX support dt-bindings: media: Add DT bindings for TI CSI2RX driver media: cadence: csi2rx: Add wrappers for subdev calls media: cadence: csi2rx: Fix stream data configuration media: cadence: csi2rx: Set the STOP bit when stopping a stream media: cadence: csi2rx: Soft reset the streams before starting capture media: cadence: csi2rx: Add external DPHY support phy: cdns-dphy: Add Rx support phy: cdns-dphy: Allow setting mode phy: cdns-dphy: Prepare for Rx support dt-bindings: phy: Convert Cadence DPHY binding to yaml phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes arm64: dts: ti: k3-am642-sk: Disable ADC arm64: dts: ti: k3-am642-evm: Mark ADC as reserved Signed-off-by:
LCPD Auto Merger <lcpd_integration@list.ti.com>
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This is the CSI2RX V4L2 driver which enables CSI2RX capture on J721E. Enable its dependencies and then enable it as a module. Signed-off-by:
Pratyush Yadav <p.yadav@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com>
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Some data might be stuck in the DMA pipeline because the application does not tell us how many frames it wants to capture. So there will always be some time delay between the application requesting the last frame it needs and stopping the stream which will stop DMA. Drain that data so it does not corrupt the next frame captured when the stream is re-started later. Marking this as a hack for now because it is not clear yet whether this is a hardware problem or a software problem. If it does turn out to be a hardware problem, it can be presented as a workaround instead. Signed-off-by:
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The subdevice power needs to be turned on before the stream is started. Otherwise it might not be in the proper state to stream the data. For some reason, it is observer with OV5640 that turning the power off when stopping the stream causes the next stream to freeze infinitely. So leave it on for now until this issue is root caused. Signed-off-by:
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Add nodes for Cadence CSI2RX, DPHY, and TI's CSI2RX wrapper. Also add nodes for OV5640 which is the camera the drivers have been tested with. Signed-off-by:
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The CSI2RX subsystem uses PSI-L DMA to transfer frames to memory. It can have up to 32 threads but the current driver only supports using one. So add an entry for that one thread. Signed-off-by:
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TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate capture over a CSI-2 bus. The Cadence CSI2RX IP acts as a bridge between the TI specific parts and the CSI-2 protocol parts. TI then has a wrapper on top of this bridge called the SHIM layer. It takes in data from stream 0, repacks it, and sends it to memory over PSI-L DMA. This driver acts as the "front end" to V4L2 client applications. It implements the required ioctls and buffer operations, passes the necessary calls on to the bridge, programs the SHIM layer, and performs DMA via the dmaengine API to finally return the data to a buffer supplied by the application. Signed-off-by:
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TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate capture over a CSI-2 bus. The TI CSI2RX platform driver glues all the parts together. Signed-off-by:
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When this bridge driver is being user by another platform driver, it might want to call subdev operations like getting format, setting format, enumerating format codes, etc. Add wrapper functions that pass that call through to the sensor. Currently wrappers are added only for the ops used by TI's platform driver. More can be added later as needed. Signed-off-by:
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Firstly, there is no VC_EN bit present in the STREAM_DATA_CFG register. Bit 31 is part of the VL_SELECT field. Remove it completely. Secondly, it makes little sense to enable ith virtual channel for ith stream. Sure, there might be a use-case that demands it. But there might also be a use case that demands all streams to use the 0th virtual channel. Prefer this case over the former because it is less arbitrary and also makes it very clear what the limitations of the current driver is instead of giving a false impression that multiple virtual channels are supported. Signed-off-by:
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The stream stop procedure says that the STOP bit should be set when the stream is to be stopped, and then the ready bit in stream status register polled to make sure the STOP operation is finished. Signed-off-by:
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This resets the stream state machines and FIFOs, giving them a clean slate. On J721E if the streams are not reset before starting the capture, the captured frame gets wrapped around vertically on every run after the first. Signed-off-by:
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Some platforms like TI's J721E can have the CSI2RX paired with an external DPHY. Add support to enable and configure the DPHY using the generic PHY framework. Get the pixel rate and bpp from the subdev and pass them on to the DPHY along with the number of lanes. All other settings are left to their default values. Signed-off-by:
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The Cadence DPHY can be used to receive image data over the CSI-2 protocol. Add support for Rx mode. The programming sequence differs from the Tx mode so it is added as a separate set of hooks to isolate the two paths. The PHY is in Tx mode by default and it needs to be set in Rx mode by setting the submode to PHY_MIPI_DPHY_SUBMODE_RX in the set_mode() callback. Signed-off-by:
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Allow callers to set the PHY mode. The main mode should always be PHY_MODE_MIPI_DPHY but the submode can either be PHY_MIPI_DPHY_SUBMODE_RX or PHY_MIPI_DPHY_SUBMODE_TX. Update the ops based on the requested submode. Signed-off-by:
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The Rx programming sequence differs from the Tx programming sequence. Currently only Tx mode is supported. Move all the Tx related parts into a set of Tx-specific hooks that are then called by the main PHY framework hooks. This way when Rx support is added all that is needed to be done is to plug in the Rx hooks. The clocks "psm" and "pll_ref" are not used by the Rx path so make them optional in the probe and then check if they exist in the power_on() hook. Signed-off-by:
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Convert Cadence DPHY binding to YAML. While here, make the clocks optional and add an optional "power-domains" property. Signed-off-by:
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As some D-PHY controllers support both Rx and Tx mode, we need a way for users to explicitly request one or the other. For instance, Rx mode can be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI. Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY. The default (zero value) is kept to Tx so only the rkisp1 driver, which uses D-PHY in Rx mode, needs to be adapted. Signed-off-by:
Paul Kocialkowski <paul.kocialkowski@bootlin.com> Signed-off-by:
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Vignesh Raghavendra authored
ADC pins are not brought out on SK EVM. So keep it disabled. Signed-off-by: -
Vignesh Raghavendra authored
ADC is used by software running on R5 by default. Therefore mark the node as reserved in Linux DT. Signed-off-by:
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- Feb 17, 2021
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.4.y * 'connectivity-ti-linux-5.4.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : net: ethernet: ti: am65-cpsw: add mqprio qdisc offload in channel mode net: ethernet: ti: am65-cpsw: add .ndo to set dma per-queue rate net: ethernet: ti: am65-cpsw: enable p0 rx_vlan_remap Revert "HACK: arm64: dts: ti: k3-j7200-common-proc-board: Disable PCIe and SERDES" phy: cadence-torrent: Do not configure SERDES if it's already configured phy: cadence-torrent: Group reset APIs and clock APIs Signed-off-by:
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This patch add MQPRIO Qdisk offload in full 'channel' mode which allows not only setup pro:tc mapping, but also configure TX shapers on external port fifos. The K3 CPSW MQPRIO Qdisk offload is expected to work with VALN/priority tagged packets and not-tagged packets have to be mapped only to TC0. - TX traffic classes must be rated starting from TC that has highest priority and with no gaps - Traffic classes are used starting from 0, that has highest priority - min_rate defines Committed Information Rate (guaranteed) - max_rate defines Excess Information Rate (non guaranteed) and offloaded as (max_rate[i] - tcX_min_rate[i]) - VALN/priority tagged packets mapped to TC0 will exit switch with VALN tag priority 0 The configuration example: ethtool -L eth1 tx 5 ethtool --set-priv-flags eth1 p0-rx-ptype-rrobin off tc qdisc add dev eth1 parent root handle 100: mqprio num_tc 3 \ map 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 \ queues 1@0 1@1 1@2 hw 1 mode channel \ shaper bw_rlimit min_rate 0 100mbit 200mbit max_rate 0 101mbit 202mbit tc qdisc replace dev eth2 handle 100: parent root mqprio num_tc 1 \ map 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 queues 1@0 hw 1 ip link add link eth1 name eth1.100 type vlan id 100 ip link set eth1.100 type vlan egress 0:0 1:1 2:2 3:3 4:4 5:5 6:6 7:7 In the above example two ports share the same TX CPPI queue 0 for low priority traffic. The 3 traffic classes defined for eth1 which are mapped to: TC0 - low priority, TX CPPI queue 0 -> ext Port 1 fifo0, no rate limit TC1 - prio 2, TX CPPI queue 1 -> ext Port 1 fifo1, CIR=100Mbit/s, EIR=1Mbit/s TC2 - prio 3, TX CPPI queue 2 -> ext Port 1 fifo2, CIR=200Mbit/s, EIR=2Mbit/s Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by:
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This patch allows to rate limit TX queues (DMA) for cpsw interface by configuring the rate in absolute Mb/s units per TX queue. Example: ethtool -L eth0 tx 4 echo 100 > /sys/class/net/eth0/queues/tx-0/tx_maxrate echo 200 > /sys/class/net/eth0/queues/tx-1/tx_maxrate echo 50 > /sys/class/net/eth0/queues/tx-2/tx_maxrate echo 30 > /sys/class/net/eth0/queues/tx-3/tx_maxrate Signed-off-by: -
By default the tagged ingress packets to the switch from P0 got internal switch priority assigned equal to the DMA CPPI channel number they came from unless CPSW_P0_CONTROL_REG.RX_REMAP_VLAN. it causes issues with applying QoS policies and mapping packets on external port fifos, because the default configuration is vlan_aware and DMA CPPI channels are shared between all external ports. Hence enable CPSW_P0_CONTROL_REG.RX_REMAP_VLAN so packet will preserve internal switch priority assigned following the VLAN(priority) tag no matter through which DMA CPPI Channels packets enter the switch. Signed-off-by:
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Enable PCIe and SERDES, since multi-link support is added in u-boot and the changes adapted in both kernel and ethernet firmware. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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Do not configure SERDES if it's already configured. Signed-off-by:
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No functional change intended. Group reset APIs and clock APIs in preparation for adding support to skip configuration if the SERDES is already configured by bootloader. Signed-off-by:
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- Feb 16, 2021
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LCPD Auto Merger authored
TI-Feature: connectivity TI-Branch: connectivity-ti-linux-5.4.y * 'connectivity-ti-linux-5.4.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/connectivity : arm64: dts: ti: k3-am642-sk: Add OSPI DT node arm64: dts: ti: k3-am642-sk: Add CPSW DT nodes arm64: dts: ti: k3-am642-sk: Enable USB Super-Speed HOST port arm64: dts: ti: k3-am642-sk: Enable WLAN connected to SDHCI0 PCI: cadence: Retrain Link to work around Gen2 training defect Signed-off-by:
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LCPD Auto Merger authored
TI-Feature: platform_base TI-Branch: platform-ti-linux-5.4.y * 'platform-ti-linux-5.4.y' of ssh://bitbucket.itg.ti.com/lcpdpublicdom/platform : dmaengine: ti: k3-udma: Fix NULL pointer dereference error arm64: dts: ti: k3-j7200-mcu-wakeup: Drop obsolete ti,sci-rm-range-girq arm64: dts: ti: k3-j721e-mcu-wakeup: Drop obsolete ti,sci-rm-range-girq Signed-off-by:
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- Feb 11, 2021
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Vignesh Raghavendra authored
AM642 SK has S28HS512T flash connected OSPI controller. Add DT entries for the same. Signed-off-by:
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Vignesh Raghavendra authored
AM642 SK board has 2 CPSW ports. Add DT entries for the same. Also add timesync_router DT node. Signed-off-by: -
Enable USB Super-Speed HOST port. Signed-off-by:
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WL1837 module is connected to SDHCI0 in AM642 SK. Enable it here. Signed-off-by:
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Cadence controller will not initiate autonomous speed change if strapped as Gen2. The Retrain Link bit is set as quirk to enable this speed change. Signed-off-by:
Nadeem Athani <nadeem@cadence.com> Signed-off-by:
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by:
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- Feb 10, 2021
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Kishon Vijay Abraham I authored
bcdma_get_*() and udma_get_*() checks if bchan/rchan/tchan/rflow is already allocated by checking if it has a NON NULL value. For the error cases, bchan/rchan/tchan/rflow will have error value and bcdma_get_*() and udma_get_*() considers this as already allocated (PASS) since the error values are NON NULL. This results in NULL pointer dereference error while de-referencing bchan/rchan/tchan/rflow. Reset the value of bchan/rchan/tchan/rflow to NULL if the allocation actually fails. Fixes: 01779473 ("dmaengine: ti: k3-udma: Initial support for K3 BCDMA") Fixes: 25dcb5dd ("dmaengine: ti: New driver for K3 UDMA") Signed-off-by:
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Suman Anna authored
The property 'ti,sci-rm-range-girq' is obsolete and was replaced with the equivalent property 'ti,interrupt-ranges'. This property was erroneously added in the Wkup GPIO Interrupt Router node. Drop this. Fixes: 86eb634b ("arm64: dts: ti: k3-j7200: Add GPIO interrupt routers") Signed-off-by:
Suman Anna <s-anna@ti.com>
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Suman Anna authored
The property 'ti,sci-rm-range-girq' is obsolete and was replaced with the equivalent property 'ti,interrupt-ranges' in commit 05d9d8fb ("arm64: dts: k3-j721e: ti-sci-inta/intr: Update to latest bindings"). This property should have been deleted but was missed out in the Wkup GPIO Interrupt Router node. Fix this now. Signed-off-by:
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- Feb 08, 2021
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LCPD Auto Merger authored
TI-Feature: rpmsg TI-Branch: rpmsg-ti-linux-5.4.y-intg * 'rpmsg-ti-linux-5.4.y-intg' of git://git.ti.com/rpmsg/rpmsg : arm64: dts: ti: k3-am642-sk: Reserve some on-chip SRAM for R5Fs arm64: dts: ti: k3-am642-sk: Reserve memory for IPC between RTOS cores arm64: dts: ti: k3-am642-sk: Add DDR carveout memory nodes for R5Fs arm64: dts: ti: k3-am642-sk: Add mailboxes to R5Fs arm64: dts: ti: k3-am642-sk: Add IPC sub-mailbox nodes Signed-off-by:
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Suman Anna authored
Reserve some portions of the MAIN domain on-chip SRAM for use by various R5F cores on AM642 SK board. A bank (256 KB) each is reserved from the on-chip SRAM for each R5F core. This is done through specific child SRAM nodes in the board dts file. The memory regions are also assigned to each R5F remoteproc node using the sram property. The reserved SRAM banks are as follows for each core: Main R5FSS0 Core0 : OCSRAM1 Main R5FSS0 Core1 : OCSRAM2 Main R5FSS1 Core0 : OCSRAM3 Main R5FSS1 Core1 : OCSRAM4 The addresses chosen are the same as the respective processors on the AM64x EVM board to maintain firmware compatibility between the two boards. Please also see commit d4175486 ("arm64: dts: ti: k3-am642-evm: Reserve some on-chip SRAM for R5Fs"). Tested-by:
Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by:
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Suman Anna authored
Add a reserved memory node to reserve a portion of the DDR memory to be used for performing inter-processor communication between all the remote processors running RTOS or baremetal on the TI K3 AM642 SK board. 8 MB of memory is reserved for this purpose, and this accounts for all the vrings and vring buffers between all the possible pairs of remote processors. The reserved memory set aside is the same as the respective carveout on the AM64x EVM board to maintain firmware compatibility between the two boards. Please see commit bfe19680 ("arm64: dts: ti: k3-am642-evm: Reserve memory for IPC between RTOS cores"). Tested-by:
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